A famous formula for π: π/4 = 1 − 1/3 + 1/5 − 1/7 + … This comes from a trigonometry formula: arctan(x) = x − x³/3 + x⁵/5 − x⁷/7 + … Putting x = 1 gives the series for π/4. This result was discovered independently by: Gottfried Wilhelm Leibniz (1673), James Gregory (1671), Nilakantha Somayaji (around 1500, in Tantrasangraha).

🇪🇸 SPAIN vs BELGIUM 🇧🇪 All-Time Head-to-Head (22 matches) • Spain: 12 wins • Draws: 5 • Belgium: 5 wins 1921: Spain 2-0 Belgium 1923: Spain 0-1 Belgium 1949: Spain 1-1 Belgium 1951: Spain 3-3 Belgium 1953: Spain 3-1 Belgium 1957: Spain 5-0 Belgium 1962: Spain 1-1 Belgium 1963: Spain 1-2 Belgium 1968: Spain 1-1 Belgium 1969: Spain 1-2 Belgium 1980: Spain 1-2 Belgium 1981: Spain 2-0 Belgium 1986: Spain 3-0 Belgium 1986: Spain 4-5 Belgium (World Cup QF – Belgium won on pens) 1990: Spain 2-1 Belgium 1994: Spain 4-1 Belgium 1995: Spain 1-1 Belgium 2004: Spain 2-0 Belgium 2005: Spain 2-0 Belgium 2008: Spain 2-1 Belgium 2009: Spain 5-0 Belgium 2016: Spain 2-0 Belgium

📌 VI. Trigger Matrix (V2.0 – Observation Status Log) Observation Item Current Value Threshold Status Consecutive Days/Trend Super-Capital Concentration Risk 9.3 8.0 ESCALATION ↑ 1 day (new) AI Governance Risk 8.8 8.0 ESCALATION ↑ 1 day (new) Resilience Ratio 0.63 0.70 ESCALATION ↑ 4 days US-Iran Deal Signing Status 接近 Formal Signing WATCH — Brent Crude Oil Price 3-mo low — THRESHOLD_CROSSED 1 day New Ebola Health Zone (DRC) Confirmed spread — THRESHOLD_CROSSED 3 days EU Accession Talks Launched — THRESHOLD_CROSSED 1 day Items Near Threshold (Elevated Observation): Observation Item Current Value Threshold Current Status • Formal signing of US-Iran deal 接近 Formal Signing ALERT • SpaceX market cap stability Above $2T Drop below $2T WATCH • OpenAI probe scope expands Multi-state Federal involvement ALERT • G7 Summit statements on AI & trade 即将 held Substantive regulatory共识 WATCH • Cross-border Ebola spread Risk rising First邻国 confirmed case ALERT • Clustered cases in fan zones No reports Confirmed cluster transmission WATCH --- 📅 VII. Key Observation List for the Next 72 Hours Grade A Observations (High Impact): Observation Item Potential Impact if Triggered 1. Formal signing of US-Iran MOU Geopolitical entropy pressure declines further, but execution risk仍需 assessed. 2. SpaceX market cap stability above $2T Test of sustainability for super-capital concentration narrative. 3. OpenAI probe expands to federal level Potential further upgrade to AI governance risk level. 4. G7 Summit statements on AI & trade First collective test of institutional response capacity. Grade B Observations (Medium Impact): Observation Item 1. Expansion of Ebola outbreak zone in DRC 2. Subsequent日程 for EU accession negotiations 3. Public health data during FIFA World Cup --- 📜 VIII. CRI Calculation Summary (V1.6) Variable Weight Risk Score Weighted Contribution V_capital 20% 9.3 1.86 V_tech 18% 8.8 1.58 V_inst 18% 8.1 1.46 V_geo 15% 7.5 1.13 V_human 10% 7.6 0.76 V_expansion 8% 7.9 0.63 V_market 6% 7.2 0.43 V_energy_price 5% 6.5 0.33 Total 100% CRI = 8.2 Calibration Notes: Added V_capital variable (weight 20%) to reflect super-capital concentration as a new structural risk dimension. V_tech上调 to 8.8 (AI governance race launch). V_geo下调 to 7.5 (US-Iran deal接近, declining war risk). --- 📌 IX. Structural Conclusion On June 13, 2026, the global civilizational system's Resilience Ratio remains below the 0.70警戒线 for the fourth consecutive day. What is most worth recording today is not war – but the first time in human civilization that private wealth approaches the GDP of a中等发达国家. When a single entrepreneur owns a satellite network, rocket system, AI platform, energy network, financial capital, and global data流入口, civilization is entering a new organizational form: Transitioning from nation-state-led civilization to platform-infrastructure-led civilization. If the core question of the 20th century was "How to constrain state power?", then the core question of the latter half of the 21st century may well become "How to govern super-platform power."

World Currencies vs. the U.S. Dollar One-Year Change As of June 30, 2026: 🇨🇴 Colombian peso: +19.2% 🇮🇱 Israeli shekel: +13.2% 🇭🇺 Hungarian forint: +8.9% 🇿🇦 South African rand: +8.1% 🇲🇽 Mexican peso: +7.7% 🇨🇳 Chinese yuan: +5.6% 🇦🇺 Australian dollar: +5.2% 🇧🇷 Brazilian real: +5.2% 🇲🇾 Malaysian ringgit: +3.1% 🇳🇴 Norwegian krone: +1.8% 🇨🇱 Chilean peso: +1.0% 🇪🇬 Egyptian pound: +0.8% 🇭🇰 Hong Kong dollar: +0.1% 🇦🇪 UAE dirham: 0.0% 🇶🇦 Qatari riyal: 0.0% 🇸🇦 Saudi riyal: -0.2% 🇷🇺 Russian ruble: -0.4% 🇨🇿 Czech koruna: -1.1% 🇸🇬 Singapore dollar: -1.7% 🇨🇭 Swiss franc: -1.8% 🇹🇭 Thai baht: -2.3% 🇸🇪 Swedish krona: -2.4% 🇪🇺 Euro: -3.0% 🇩🇰 Danish krone: -3.1% 🇬🇧 Pound sterling: -3.4% 🇨🇦 Canadian dollar: -4.1% 🇵🇱 Polish złoty: -4.2% 🇳🇿 New Zealand dollar: -6.8% 🇹🇼 Taiwan dollar: -8.2% 🇵🇭 Philippine peso: -8.2% 🇮🇩 Indonesian rupiah: -9.3% 🇮🇳 Indian rupee: -9.4% 🇯🇵 Japanese yen: -11.3% 🇰🇷 South Korean won: -12.6% 🇹🇷 Turkish lira: -14.6% 🇦🇷 Argentine peso: -18.9% Source: Deutsche Bank, Bloomberg Finance LP.

🚨 SlowMist TI Alert 🚨 The Shai-Hulud malware has resurfaced via the npm account atool(i@hust.cc), with over 600 malicious versions published. Notably, high-download packages such as size-sensor@1.1.4 (4.2M dl/mo), echarts-for-react@3.1.7 (3.8M dl/mo), and @antv/scale@0.6.2 (2.2M dl/mo) are at elevated risk. The attack carries risks: 1. AI agent hijacking: Claude Code, Codex, and VS Code tasks can trigger a Bun bootstrapper that re-executes the malicious payload. 2. Credential harvesting: The malware collects credentials from cloud services, GitHub, npm, local environments, and CI/CD pipelines. Using ^ to specify version ranges may cause npm to automatically install versions that have been compromised or contain security risks. Detection & Mitigation Measures: • Audit dependencies for any package published by atool (i@hust.cc) and check for suspicious preinstall scripts • Remove compromised packages and rotate all exposed credentials • Inspect CI/CD pipelines and local Node.js projects for malicious hooks or workflows • Revert to safe package versions or known-good dependencies ⚠️ Critical Action: Treat any system with affected packages as potentially compromised. Apply mitigation steps immediately.

U.S. FACTORY ORDERS BEAT EXPECTATIONS U.S. factory orders rose 0.9% in July, beating expectations for a 0.6% increase and rebounding from June’s decline. Orders excluding transportation climbed 0.6%, while orders excluding defense jumped 1.0%. Durable goods orders were confirmed at +1.1%, while nondurable goods orders increased 0.7%. However, computers and electronic products orders fell 1.1%, reversing June’s 3.1% gain. Overall, the data points to stronger U.S. manufacturing demand in July, despite weakness in the technology segment.

Hardy and Ramanujan’s most famous joint paper was in the theory of partitions, the ways of representing a given whole number n as the sum of positive whole numbers. The number 5, for example, can be “partitioned” seven ways: 5 = 5 5 = 4 + 1 5 = 3 + 2 5 = 3 + 1 + 1 5 = 2 + 2 + 1 5 = 2 + 1 + 1 + 1 5 = 1 + 1 + 1 + 1 + 1 As n grows, the number of partitions balloons. For n = 10, there are 42. For n = 50, there are 204,226. For n = 100, there are 190,569,292. And for n = 200 there are 3,972,999,029,588. In 1918, in a forty-page paper on partition theory, Hardy and Ramanujan offered a surprisingly accurate asymptotic formula for the number of partitions of an integer n. In 1942, Erdős was able to show that Hardy and Ramanujan didn’t need to use heavy machinery to deduce the first term of their formula, that the term could be found by “elementary” methods. Elementary techniques are not necessarily simpler. In this context, elementary means that the proof of the formula relies on a restricted set of numbers, the so-called real.

I've been discussing Huawei's τ scaling (temporal scaling) with people recently, and noticed the conversation tends to stay at the surface level without reaching its substance — likely because many participants don't come from an EE background and aren't familiar with the classical meaning of τ in circuit theory. The very first time constant you learn in a circuits course is τ = RC: the resistance of a wire multiplied by its capacitance gives the order of magnitude of the time a signal needs to traverse that wire. The longer the wire, the greater the resistance and capacitance, and the slower the signal. Within this framework, the past sixty years of geometric scaling are reinterpreted as one particular implementation of temporal scaling. Transistors were shrunk to shorten switching delay; circuits were packed more tightly to shorten metal interconnects and reduce signal propagation delay. Geometric scaling was only ever the means — compressing delay was always the end. Huawei's thesis is that once geometric scaling stalls, you find other ways to keep compressing delay. As it happens, He Tingbo's τ scaling paper released its v2 a couple of days ago, expanding from 16 to 23 pages. I compared the two versions: the data and conclusions are unchanged. The additions are essentially responses to several points of criticism the industry raised about v1. Three are worth discussing. The most important addition is the test evidence now backing the previously bare claim of "41% energy efficiency improvement." In v1, that number had no baseline and no test conditions — the most obvious target for scrutiny. V2 supplies a full comparison table. The baseline is the 2025 Kirin 9030 Pro. Both chips use the same mature process node; the key difference is that the baseline uses a conventional planar design, while Kirin 2026 folds critical paths across two vertically bonded wafers. Folding shortens interconnects and reduces interconnect delay. The timing margin freed up on the critical path translates directly into a higher maximum clock frequency: 3.1 GHz at 1.1 V supply, 13% above the baseline. The "41% energy efficiency improvement" comes from a separate operating point specifically configured for an iso-performance comparison: voltage scaled down to 0.9 V, frequency scaled down to 2.5 GHz, with measured power at 25°C coming in at 0.59× the baseline. A back-of-the-envelope estimate checks out: dynamic power scales roughly with the square of supply voltage, so an 18% voltage reduction contributes about one-third of the power drop from the square term alone. Factor in the 9% frequency reduction and the interconnect capacitance eliminated by folding, and you land right around 0.59×. So the precise meaning of "41% energy efficiency improvement" is power reduction at iso-performance. In essence, the timing margin gained from folding is traded for lower power consumption; the efficiency gain comes from logic folding. As a side note, v2 also reports that power density after dual-layer stacking is actually 5.6% lower than the baseline. The second addition addresses the question peers are most likely to ask: 3D stacking has been around for years — AMD's 3D V-Cache and Intel's Foveros are both in volume production — so what's new about LogicFolding? To understand the paper's answer, you first need to know how two layers of silicon communicate. They rely on inter-layer bond pads, which function like elevators connecting the upper and lower floors. In prior production 3D stacking, bond pad pitch ranges from 9 μm to tens of micrometers, yielding roughly ten thousand connections per square millimeter — enough to attach a bus to an entire cache block. So the established design approach has been to move complete functional blocks wholesale onto the upper tier. AMD, for example, stacks an entire cache die on top of a processor die; the two tiers are designed independently and connected through an interface. But inside a chip, a single square millimeter contains hundreds of millions of transistors. If you want adjacent logic gates to sit on different tiers — one on top, one on the bottom — that connection density falls far short. Kirin 2026 brings bond pad pitch down to 1.5 μm, yielding 440,000 connections per square millimeter. That approaches the density of the top-level metal wiring inside a chip. Routing a signal across tiers costs roughly the same as routing it across metal layers within a single die. At this point, the two silicon layers merge into a single entity in the circuit sense. EDA tools can decide at the individual logic-gate level which gate goes on which tier, handing the problem to algorithms for global optimization — a completely different degree of design freedom from what came before. The paper also explains why they didn't take the more aggressive route of fabricating a second device layer directly on top of the first. That approach offers the finest inter-layer connectivity, but manufacturing the second layer requires high temperatures that damage the already-completed first layer. It isn't production-viable today. The third addition is thermal management. Vertical stacking significantly increases thermal density per unit area, and the lower die's heat dissipation path is blocked by the upper die. This is the first objection anyone raises about 3D stacking, and v1 did not address it in depth. V2 openly acknowledges that thermal management remains a key challenge for the LogicFolding architecture. The countermeasure is thermally-aware partitioning and floorplanning: during the design phase, high-power circuits are excluded from folding candidates, and the floorplan avoids placing high-power blocks in vertical adjacency to prevent hotspot superposition. Whether this strategy is a set of manually imposed engineering constraints or has already been codified into an automated flow within their internal EDA tools, the paper does not say. It only identifies a multi-physics tool chain as the single most important investment for the next decade. Combined with the measured data showing power density 5.6% below the baseline at the iso-performance operating point, the thermal concern has at least received a direct response. That said, this approach is fundamentally avoidance-based. As stacking grows to three or four tiers, the design space eligible for folding will be progressively squeezed by thermal constraints — a boundary the paper does not explore. Additionally, v2 includes a cross-sectional micrograph of the bond interface between the two wafers and explicitly states that wafer-on-wafer hybrid bonding is used. This spec is worth benchmarking against the industry: 1.5 μm pitch wafer-to-wafer hybrid bonding on a production logic chip has no precedent. TSMC's SoIC is currently in production at 6 μm pitch; Intel's Foveros Direct is at 9 μm. Impressive, to say the least. After comparing the two versions, I'm left with two questions. One is about equipment: who supplied the bonding tools capable of this spec? The paper says only that it is the result of years of process development across a multi-vendor ecosystem. The other is about EDA: designing two wafers as a single chip is beyond what any commercially available EDA tool can do today. The paper acknowledges this, stating only that methodological details will be "published within months." Yet the frequency table shows that the 2027-generation Kirin at 3.39 GHz is already tagged as having physical silicon, meaning this toolchain was up and running inside Huawei long ago — and has been validated on at least two product generations. My personal guess is that this EDA capability was built in-house by Huawei. If anyone has insight on this, I'd welcome the discussion.