I went through TSMC's 2029 packaging roadmap looking for what got cut in the write-ups. The two lines that got cut are the ones with a bill attached. The presentation was at a SEMICON Taiwan forum on 1 September, by TSMC's advanced packaging R&D director. What travelled: CoWoS package size going from 3.3 reticles to more than 14 by 2029, compute transistors inside one package up about 48 times, and HBM bandwidth per package up more than 34 times, from eight HBM3 stacks to twenty-four HBM5E. What did not travel is on the same slides. Package power on that path goes from about 600W to 4,100W, and over the same stretch power delivery losses rise more than fivefold. That second one is the sentence worth stopping on. Not the power the thing draws, the power you lose putting it in. I checked the leading English write-up word by word before saying this: it contains none of 600W, 4,100W, power delivery, underfill, or microbump. The cooling answer was laid out as a ladder. Today, a cold plate on top with thermal interface materials underneath. Next, microchannels built into the package lid to shorten the path. After that, jet impingement and two-phase boiling. Microchannel cooling is now on the R&D roadmap, and the stated difficulty is manufacturing, because cutting coolant channels into an expensive chip means a small error scraps it. The other thing that did not travel is the bump. TSMC is staying on conventional microbumps for HBM rather than moving to hybrid bonding, and has asked suppliers to develop roughly 5 micron class bumps. Korean and Japanese suppliers have started. Mass production is estimated for the second half of 2028. And the reported gate is not the bump at all. It is the underfill that has to hold a 5 micron bump and pass qualification with it. So the published roadmap is a foundry document, and underneath it sit three schedules that belong to other people: cooling, power delivery, and bonding materials. The first set of numbers tells you how big the package gets. The second set tells you who has to spend to make it work. 3711 TT and $AMKR on assembly, $TER and $FORM on test, $MU and $SKHY on the twenty-four stacks, and an underfill supply chain almost nobody covers. What I would watch is the underfill qualification, not the bump pitch. That is the date that moves everything else.

Kioxia just told its sales team to stop pushing NAND higher on AI data-center buyers. According to Bloomberg, CEO Hiroo Ota, in office since April, ordered staff not to demand another large increase in those talks. He did not rule out future hikes. For now the job is to hold the high level already in the book. “If we raise prices too much we hurt our own market and growth. Hyperscalers have finite budgets.” Second-quarter NAND ASP rose 70% from the first quarter. The quarter before that more than doubled. Ota said another 70% step is unlikely. Keep squeezing and the labs cut capex. That would cut the cycle he wants to keep. Demand itself is still firm. Some customers want supply contracts out to 2030. Holding the line is also a way to lock those multi-year books. The print already shows the squeeze. April–June net profit was 869 billion yen, about $5.5 billion, 48 times a year earlier. Sales were 1.77 trillion yen, more than four times. The stock is about 18 times last year’s level. On SK Hynix, Ota closed the door. Antitrust plus the Sandisk joint NAND plants make a formal tie-up unrealistic, he said. The two are not talking joint production. That answers SK Hynix CEO Kwak Noh-jung’s August comment that closer work was under review. High and stable beats one more 70% print. If Kioxia will not take the last dollar, do Samsung and Micron still try to, or does the NAND ceiling get set in Tokyo? $MU