# ADK 2.0の便利だけど知られていない機能
🌍 エージェントの評価で「実際のユーザーとの会話」を再現できたら、テストの質が格段に上がると思いませんか?
ADK 2.0のユーザーシミュレーション機能は、多様なペルソナを持つ仮想ユーザーとの会話を動的に生成し、エージェントの応答品質を体系的に評価できる仕組みです。
📌 タイトル:ユーザーシミュレーション (User Simulation)
🔗 URL:
🧩 概要
ユーザーシミュレーションは、エージェント評価のために動的な会話プロンプトを自動生成する機能です。`ConversationScenario` を定義し、`starting_prompt`(会話の開始メッセージ)、`conversation_plan`(会話の進行計画)、`user_persona`(ユーザーの振る舞い)を指定することで、現実的な対話パターンを再現します。組み込みペルソナとして、EXPERT(詳細志向で誤りを指摘する)、NOVICE(指示を待つ受動的なユーザー)、EVALUATOR(詳細志向だが誤りの指摘はしない)の3種が用意されています。
🛠 使い方
CLIから `adk eval_set generate_eval_cases` コマンドで評価ケースを生成できます。カスタムペルソナを作成する場合は `UserPersona` クラスを使います。
```python
from google.adk.evaluation.conversation_scenarios import ConversationScenario
from google.adk.evaluation.simulation.user_simulator_personas import (
UserBehavior,
UserPersona,
)
# カスタムペルソナの定義
impatient_user = UserPersona(
id="IMPATIENT",
description="短い応答を好み、長い説明には不満を示す",
behaviors=[
UserBehavior(
name="Short responses",
description="短く、ときに不完全な応答をする",
behavior_instructions=["応答は10語以内にする", "丁寧な言い回しは省く"],
violation_rubrics=["応答が10語を超えている"],
)
],
)
# シナリオの定義
scenario = ConversationScenario(
starting_prompt="旅行の予約を手伝ってください",
conversation_plan="目的地→日程→予算の順に確認し、最終的に予約を完了する",
user_persona=impatient_user
)
```
🏗 本番システムへの組み込み方
・CI/CDパイプラインに評価シナリオを組み込み、エージェント更新時に自動でリグレッションテストを実行する
・EXPERT/NOVICE/EVALUATORの3ペルソナを使い分けて、異なるユーザー層での応答品質を網羅的に検証する
・`conversation_plan` を業務シナリオに合わせて設計し、実際の利用パターンに近い評価を行う
・カスタムペルソナを作成して、自社サービス特有のユーザー行動パターンをシミュレートする
💡 ユースケース
🧪 新しいプロンプトやモデルへの変更後に、会話品質のリグレッションを自動検出する
👥 初心者ユーザーと上級者ユーザーで異なる応答戦略が機能するか検証する
📊 複数シナリオを一括実行して、エージェントの弱点を体系的に洗い出す
🔄 会話の途中で話題が変わるケースや、曖昧な質問への対応力を評価する
⚠️ 注意点
シミュレーションはLLMベースで生成されるため、同一シナリオでも実行ごとに会話の展開が微妙に異なる場合があります。評価の再現性を確保するには、複数回実行して統計的に判断することをお勧めします。また、組み込みペルソナはそれぞれ異なる振る舞いをするため、評価目的に合ったペルソナを選択してください。
✨ ユーザーシミュレーションを活用することで、実ユーザーを巻き込まずにエージェントの対話品質を継続的に改善できます。多様なペルソナでの評価を習慣化しましょう。
#
ADK# #
AIAgent#
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Breaking down TSMC's glass core substrate slide
On June 11, at JPCA Show 2026 in Japan, TSMC gave a roughly 40-slide presentation titled "Advanced Packaging Technology Essential to the Evolution of AI" (AIの進化に不可欠な先端パッケージング技術). One slide from the deck, titled "Glass Substrate Development for CoWoS," has since leaked online and widespread attention.
Here's a closer read of that slide (see attached image). I'll skip the technical background that is already widely available. One thing to flag: the "COP" on the slide does not stand for Chip-on-Package. It means Coplanarity.
▌ Key conclusions:
1. TSMC has officially announced a partnership with Ibiden and Innolux to develop a glass core substrate. The structure is a three-layer design, a glass core sandwiched between two ABF build-up layers. This is the "oS" in CoPoS.
2. The market underestimates how important the glass core substrate is. It's a must-have capability for TSMC. In other words, within CoPoS the "oS" matters more than the "CoP", which is also why, when it was tested, it was paired with the existing CoW rather than with CoP.
3. The glass core substrate costs several times more per unit than existing ABF substrates. The glass processed by Innolux is very expensive per unit and is the single most critical material. Besides Nvidia, two US-based customers have also expressed strong interest.
▌ Industry checks tied to this slide:
1. The glass core substrate shown on the slide is cut from a full-size 250×250mm one. The ABF build-up layers mainly use Ajinomoto's GL107, mixed with ABF-GCP, and were tested at 24–28 layers, which is the mainstream ABF spec for AI chips in 2027–2028.
2. The CoW used in TSMC's experiment is a test vehicle. It is sufficient to validate the most challenging mechanical-structure issues that arise when working with composite materials. Good results mean TSMC, Ibiden, and Innolux have together broken through the critical technical bottleneck.
3. Ibiden currently handles cutting the 250×250mm glass core substrate. When the 510×515mm format is used for pre-mass-production simulation in 2H27, if Ibiden still wants to reduce production complexity to protect its ultra-high gross margins, it may hand the cutting over to Innolux, which is more familiar with the properties of glass.
▌ The leaked slide shows the validation results of pairing CoW with the "oS" in CoPoS, i.e., the glass core substrate (labeled "glass-SBT" on the slide). This addresses the "Substrate mechanical and electrical Dilemma" raised on the previous slide, and it strongly underscores how important the "oS" is within CoPoS.
1. Within CoPoS, what CoP solves is production efficiency / cutting economics, which ties to cost and price. What the oS solves is warpage and durability, which determines whether the chip can be made at all, and whether it can work.
2. CoP and oS complement each other well when integrated, but looking out over the next few years their technical roles still differ. CoP is a very-nice-to-have optimization, and going without it simply means a more expensive chip. But the oS is a must-have. Without it, even being able to make a usable chip is in doubt.
3. Comparing their roles isn't about elevating oS at the expense of CoP. It comes down to the practical question of which technical piece customers are willing to pay for. Details below.
▌ The real gold here is the power integrity (PI) improvement shown on the slide. This matters a great deal to customers, and it means that once glass core substrate production stabilizes, TSMC's profitability and competitive edge should rise in tandem.
1. How it works: the glass core substrate is thin → the vertical conduction path through TGV (through-glass vias) is short → conduction-path resistance (R) and loop inductance (L) both drop → PI improves.
2. Why it matters to customers: better PI → more stable power delivery → frees up power headroom → room to integrate more transistors, or to push clock speeds higher → more AI compute.
3. For customers, production efficiency is TSMC's basic responsibility, so they won't pay extra for it. But gains in AI compute translate directly into the customer's own competitiveness and profit, so customers are willing to pay for that. This is why Nvidia is so positive on the glass core substrate.
4. For TSMC, the glass core substrate raises yield and lowers cost while also boosting both the compute and the selling price of AI chips. It's both a cost-cutting tool and a pricing lever, a plus for profitability and competitiveness alike.
5. Substrate cost currently accounts for a low single-digit percentage of an AI chip's BOM, while losses from packaging yield run roughly 5–10× the substrate cost. So even if the glass core substrate ends up costing several times more than today's, its share of the BOM stays low, and it can cut the losses from packaging yield. The high unit price is therefore not expected to dampen customers' willingness to adopt it.
▌ In the Q&A after the presentation, an audience member asked about TGV details for the glass core substrate. TSMC declined to answer on the spot, because TGV is the key technology behind the glass core substrate, and the core know-how currently sits with TSMC and Innolux. By contrast, when another attendee asked about integrating IVR, eDTC, and LSI, TSMC answered at length.
▌ According to industry checks, if all goes well, TSMC is aiming to start mass production of the glass core substrate in 4Q28–1Q29, to match the cadence of Nvidia's AI chip iterations. As a side note: the Ibiden earnings presentation slide that many people have been circulating lists the glass core substrate timeline as CY30. My read is this: Ibiden, which has always been conservative and cautious in public, has now formally put the glass core substrate on its roadmap, which further confirms the long-term trend for this technology. That said, some other details on Ibiden's slide don't fully line up with what's known in the market. For example, its reticle timeline is off from TSMC's public claims by about a generation, and the Rubin Ultra substrate size is clearly larger than the 90×90 it marked for CY26–27. It's a reminder to always cross-check across multiple sources when forecasting the future.
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