BlackRock $BLK wrapped up a $12.5 billion bond sale tied to a Meta Platforms $META data center project in Texas The 2048 note sold at a yield premium of 2.875% over 10-year Treasury yields - Bloomberg

AMD is preparing a new budget graphics card called the Radeon RX 9050 for the RX 9000 series. The card uses the Navi 44 chip with 2048 processing units and 8GB of memory but runs at lower speeds than the RX 9060 models to use less power and stay affordable. It is made for 1080p gaming and only needs a 450W power supply, for budget PCs and small cases. No official price or release date has been announced yet, but it will likely cost under 250 dollars

$MU $SKHY $DRAM $NVDA $LITE AI is still diapers According to $TSM's HPC roadmap (SEMI Taiwan today), AI compute demand growing 5x/year, creating a "compute wall" and "memory bandwidth wall." TSMC's answer is heterogeneous integration across logic, 3D packaging, and silicon photonics. Logic process: Moving fully to nanosheet architecture. After N2 and A16, TSMC targets A14 (angstrom class) in 2028 to 2029. 3D stacking (SoIC): In production since 2023 with 56x the interconnect density of traditional 2.5D. Roadmap is N2P on N3P in 2026, then A14 on A14 in 2029, shrinking bump pitch to 4.5 microns. CoWoS packaging: 5.5x reticle size in 2026 (supporting 12 HBM3E/4 stacks, yield over 98%), 9.5x reticle by 2028, and over 14x reticle with 24 HBM stacks by 2029. Combined system compute: TSMC projects SoIC plus CoWoS integration will deliver 50x the 2024 compute level by 2029. HBM4 and the memory wall: Interface bandwidth doubles to 2048 bit. Base die built on N12, cutting power over 45% and boosting bandwidth 2.5x, with a future move to N3 for further gains. Overall memory bandwidth is projected to grow 34.6x by 2029. COUPE (silicon photonics): 3D stacks the electronic die directly onto the photonic die via SoIC, with 2 to 4 micron bond pitch. At 112Gbps, transmission loss is just 0.06dB versus 1.38dB for microbumps, cutting latency to 10 to 20 nanoseconds. First 200Gbps micro-ring modulator (0.5 Tbps/mm density) ships in 2026, scaling to 4 Tbps/mm by 2030. Design enablement: TSMC is building an optical PDK for electro-optic co-simulation plus automated DRC/LVS/thermal flows to speed 3D IC and photonic design.

Qwen3.5-4B running CPU-ONLY at up to ~11+ tps on a Ryzen 5 laptop. No GPU. Running models in RAM and CPU is something the Qwen4 team is already thinking about. 💡 I built this standalone .exe because businesses are already deploying local models to save money and ensure privacy. (thumb drive friendly - just drag drop and doubleclick) My llama.cpp recipe 👉 🧠 Qwen3.5-4B Q4_K_M GGUF ⚙️ Ryzen 5 7540U — 6C/12T 🧵 --threads 9 🧵 --threads-batch 12 ⚡ --prio 2 🔄 --poll 50 📦 --batch-size 2048 📦 --ubatch-size 512 🚀 --flash-attn on 🧠 KV cache: q4_0 / q4_0 🔧 --repack 💾 --mmap 👤 --parallel 1 🚫 --device none 🚫 --gpu-layers 0 🚫 KV/op GPU offload 🚫 MTP OFF Interesting result 👉 MTP=3 was slower (~10 tps in benchmarks). Plain decode + 9 threads + Q4 KV hit ~11.4 tok/s. That's about 10% faster just from tuning llama.cpp — on a basic laptop CPU.