Google researcher @lauriewired explains how CXL could unlock the massive amount of compute sitting idle inside hyperscale data centers: "The real key comes down to when you're working in really hyper-specific fields, like high-frequency trading or game development. If you do not have these fundamentals in these hyper-specific areas, then you're going to have difficulty." "Debugging memory accesses could be data on a different system, swapped to disk, or refreshes with the memory controller causing unexpected delays. New hardware is really going to emphasize people's fundamentals here, because I'm gonna be talking over at CppCon and giving a keynote on C++ and heterogeneous memory architectures." "If you're sitting there on your computer, most of the time you're not using the majority of your compute. You have a lot of your machine sitting there idle. But put this on a really large scale hyperscalers or data centers. This wasted compute, if you multiply it over and over again, grows exponentially." "One technology I'm really excited about is CXL, Compute Express Link. Older versions was allowing you to just extend memory for a local device. But newer versions open this door to have shared memory pools that you can access between a ton of different hosts, and you can do this cache coherently." "It allows you to have read-only sections that are shared with quite low latency between multiple different hosts." @Google

Things I learned today about memory: • CXL controller companies are expanding beyond chips into AICs, pooled memory, and JBOM. Customer demand is strong. • One major challenge for SK hynix is SoC design capability. • I heard this was also related to its decision to stop developing its own CXL solution internally. • The same issue could matter for custom HBM as more logic moves into the base die. SK hynix is actively hiring to strengthen this capability. • One CXL engineer questioned whether custom memory will actually generate significantly higher profits. His view is that conventional DRAM may still have the largest profit pool. • His company is working with Penguin Solutions and expanding relationships with SK hynix and Samsung. Overall, they expect the disaggregated memory market to become much larger. I immediately put what I learned from you into practice, @kevinxu 🫡

UBS - $MRVL has the leading market share in CXL products Following our latest CPU work, we believe the CXL opportunity is inflecting with players like MRVL and ALAB positioned to benefit as we move towards the end of the decade. Cache-coherent, low-latency, high-bandwidth interconnect built on PCIe is expanding the market, and CXL is becoming a critical enabling technology. We believe MRVL has the leading market share in CXL products to date but we do see ALAB and maybe AVGO becoming larger players as the market expands, with the CXL-related ASIC attach market reaching $7–10B by 2030E given applications evolving from single-CPU memory expansion toward rack-wide and multi-rack CXL fabrics connecting CPUs and XPUs. We expect CXL revenue to reach ~$1B in C2027E for MRVL, largely driven by XPU-attach within racks, with incremental support from agentic CPU demand. CXL revenues span three categories: interconnect (legacy expander use cases), XPU-attach (newer custom hyperscaler designs, where MRVL has five programs with two major US hyperscalers including for MRVL’s Google TPU (we think)), and switching (CXL switches). The company has indicated that the bulk of the ~$1B target for CXL revenues is tied to XPU- attach sockets rather than CPU-attach, and agentic tailwinds to the CPU adoption are incremental to existing XPU-focused programs.

From Marvell’s conference call: Q: What progress are you seeing in CXL and scale-up optics? A: CXL began as a server-centric memory architecture but has ultimately proven to be ideally suited for memory expansion and inference. It is now being deployed at scale by multiple hyperscalers. Amid growing inference demand and memory scarcity, customers are revising their plans to expand their use of the technology. Marvell also secured additional design wins in the latest quarter. Scale-up optics has accelerated further from the roughly $300 million FY28 outlook provided last quarter, including $150 million from Celestial AI CPO. CPO and NPO are not an either-or choice; both will coexist. Q: How are constraints such as surging memory prices affecting design wins? A: As supply, power, and architectural constraints converge, the need for fungibility across compute, networking, and memory is increasing. The ability to execute rapidly on custom and semi-custom solutions—and modify products to adapt to evolving architectures—is a critical asset. CXL memory expansion and AI inference accelerators are representative examples. Activity is increasing significantly as the market rapidly shifts from training to inference and then to monetization. $MRVL

Meet CMM-Ax, @SKhynix's ASIC-based CXL-PNM solution developed with Marvell Technology. Designed to overcome memory bottlenecks in long-context #LLM# inference, CMM-Ax delivers up to 5.5× higher throughput than conventional GPU-only systems. #SKhynix# #CXL# #CMMAx# #PNM# #AI#