This is a good example why I continued to use cell level density but not block level density. Because when you want to use block level density compared different node, especially cross foundry comparison, too many detail you need to be considered. Like 18A vs N2 case, some people may say 18A has BSPDN so you should considered the block level density gain by BSPDN. Yes, because BSPDN move some metal layer to backside, so some dummy metal can also be placed and shared the backside space, so your device metal routine resource increase and block density may gain in some case. Actually, this block level density gain number by BSPDN is floating. Some case especially you use larger amount of HP/ UHP cell with dense power grid, this number can enlarge to ~20%. But in most case, a ~10% gain in area will be mentioned and estimated. However, if you want to compared the block level density, then many design rule detailed and DTCO you must considered. Like N2 offer NanoFlex that providing short-tall cell abutment that could yield in 15% performance gain under same area or translate to x% area gain under same performance, and 18A do not offer this DTCO until 14A. So how do you compared these block level density gain? Dummy rule constrained or dummy area reduction is another example, like Xiaomi claim 5% block level density gain by scrub line area reduction with O3 chip compared to O1 chip. So how can you confirm to add these extra 10% block level density gain by BSPDN on 18A but not considered the DTCO area gain on N2? Hence this ~10% density gain is only suit for same foundry comparison with FSPDN vs BSPDN in some applications. ( andto be mentioned, HD cell gain from BSPDN is much smaller than HP cell). So this is why I only use cell level density to compared the different node.