Samsung's custom HBM talk is great. Building a base die on leading edge node affords the following advantages: 1) The TSV PHY block gets smaller enabling more parallel TSVs 2) The D2D PHY gets smaller which means that silicon area on both the base die and the XPU gets smaller. This opens up space on XPU and base die for other functions. 3) The memory controller usually on the XPU die, can be integrated on the base die. 4) Advanced RAS functions will be integrated into the base die. Thermal, voltage, process, and aging sensors enable real-time, high-speed telemetry. The SRAM on advanced base die can be used to perform repair and correction. 5) The custom die will incorporate more proessing elements bringing some level of compute to the base die. 6) The extra space can also be used for memory extension controller so that expansions to things like HBF are possible. 7) Eventually, the plan is to stack the custom base die + hbm stack (more like 4 high due to thermals) on top of compute --> zHBM. The main thermal problem comes from D2D block, but vertical stacking means that the D2D will be more distributed (edge vs area) thereby helping thermals. 8) Samsung prefers the use of proprietary D2D, rather than UCIe because they feel UCIe is larger, and not quite energy efficienct.