Spent the last few days talking with optics folks and sitting through conference talks, industry side included. As AI models advance, hardware keeps picking up more of the upside. The evidence is simple — related government and private funding programs have exploded. More funding = a bigger industry. And that naturally pulls more students into the field. Not just Korea, the US is the same story. And once the industry grows and funding ramps, equipment orders follow. But with SiPh, it's not just any equipment that ramps. The layers where an optical dimension gets added tighten first. To play the SiPh ramp, you have to know the equipment stack. Purity of the SiPh signal rises as you go down the stack. L0. Front-end fab — litho/depo/etch $ASML, $AMAT, $LRCX, $KLAC. Biggest dollars, but photonics just rides on CMOS demand. Weak as a standalone SiPh signal. L1. Wafer-level optical + electrical probing — the real bottleneck. Coupling light into the wafer while probing electrically at the same time. FormFactor $FORM (CM300 + probe card, grating-coupler alignment). Optical alignment speed is the rate-limiting step for volume ramp. L2. Parametric / metrology layer — tunable lasers, OPM, LCA, high-speed BERT/scope for EAM/modulator bandwidth. Keysight-centric $KEYS, with Viavi $VIAV/EXFO/Anritsu alongside. L3. Burn-in / KGD / reliability — $AEHR (WaferPak/FOX). Once you go CPO, you can't let a single bad optical die into a multi-chip package, so KGD becomes mandatory. L4. Packaging / final / system-level ATE — fiber attach, optical packaging, and when volume hits, $KEYS/Advantest $ATEYY/ $TER. The bottlenecks sit at L1 (optical alignment) and L3 (KGD). The moment AI forces CPO, those two layers tighten first — and once volume breaks out, the ATE above gets pulled in next.