Papa Johns(@SVTrivo):Yeah… Anthropic just casually dropping $500–850k for a Research Engineer, Chip Design RL role. Looking at the requirements — full ASIC/FPGA flow, RTL to tape-out, UVM/formal, physical design, PPA, DFT, EDA tools, balancing research with actual silicon delivery… These are just the things I’ve been doing for years. Nice. Sometimes it’s just fun to see what compensation bands and roles these companies are putting out.

Papa Johns

@SVTrivo

Semiconductor Engineer, Ph.D. 🇰🇷🇺🇸 📍 San Jose Startup & Big Tech Vet John's Papa Silicon Valley Trivopaedia: Tech, Money, Food & Chips. Life in the SV

가입 December 2009

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Papa Johns@SVTrivo

2026.08.06 07:29

Yeah… Anthropic just casually dropping $500–850k for a Research Engineer, Chip Design RL role. Looking at the requirements — full ASIC/FPGA flow, RTL to tape-out, UVM/formal, physical design, PPA, DFT, EDA tools, balancing research with actual silicon delivery… These are just the things I’ve been doing for years. Nice. Sometimes it’s just fun to see what compensation bands and roles these companies are putting out.