A lot of CPO performance can be left on the table if the high-speed 224Gb/s+ SerDes bottlenecks data throughout in the overall electrical - optical data link. Most people hyperfocus on analyzing the performance of CPO because its components can be easily analyzed individually: EIC, PIC, laser source, modulator scheme, bonding mechanism, etc. However, high speed SerDes is often treated as a "black box" by outsiders. Inside that black box, SerDes increasingly relies on sophisticated IP blocks in specific process nodes such as ADCs, PLLs, and DSP blocks. In this post I break down a modern high-speed SerDes architecture from ISSCC and key tutorial papers. This article is intended for designers working on SerDes blocks who often don't have system context, as well as outsiders interested in learning more about SerDes from first principles.