High quality call. The expert spent 31 years at $INTC, 24 of them inside the fabs, running 24/7 operations across lithography, dry etch and thin films metals as an area manager. He traces Intel's derailment to one call: for 10nm, Intel decided it did not need EUV, despite having been one of the largest investors in ASML to create the technology. The company committed to technical specifications that could not be delivered reliably without it, then tried to hit them with quad patterning. "Despite Intel being one of the biggest investors in ASML to create EUV technology a decade earlier, by the time that technology was ready, we said, 'Nah, we don't need it.' That was a watershed decision... Yields, costs, throughput, all of it suffered." The mechanism that turned a process error into a company-level failure is the IDM coupling. Intel products depend on Intel Foundry. When 10nm underdelivered, the product line had no competitive process to design onto, and the only remedy was outsourcing, which is why a meaningful share of Intel's chiplets are built at TSMC. Low internal volume then starved the fabs of the very thing they needed to recover. His framing of the node sequence is bracing: Intel 7, Intel 4, Intel 3 and 18A were a chain in which each node inherited the unresolved problems of the one before, and 18A arrived initially without yield or parametrics. He puts the effective slip on 18A at roughly two years. Process improvement is a data-limited exercise. TSMC runs full loading for Apple, AMD and NVIDIA, which generates enormous volumes of process data, which enables fast learning cycles, which sustains leadership, which attracts the volume. Intel is fabbing almost exclusively for Intel products, and Intel products have been weak for a decade. The data turns are not there. "They're basically only fabbing for Intel products, and Intel products have been struggling. The volume of data is just not there for Intel to innovate faster... I think sometimes the reason Intel hesitates, the reason they waffle a little bit on making claims is because of this, because they just can't get the data turns fast enough to know with confidence where they're at." He flags Foveros and wafer-level packaging as equally critical to 18A and increasingly the harder problem. Panther Lake does not ship without it, and a packaging failure destroys yield at a far higher cost per unit than a front-end failure, because you are scrapping fully processed die. Lip-Bu Tan's original position was that Intel would not commit to 14A without external customers putting skin in the game. The expert's point is that this position was internally incoherent with the stated commitment to remain an IDM. If Intel does not build 14A, Intel products cannot design competitive parts, so Intel products must be allowed to outsource wafers. Do that for a couple of years and the foundry loses its largest customer and is finished. He also thinks the original statement was a strategic error in communication terms, since no prospective customer is motivated by a vendor signaling it might stop investing. "Intel products cannot design competitive products if the foundry is stuck on an old node. If Lip-Bu stuck to that initial declaration, he is then required to allow Intel products to outsource their wafers. By default, over time, not very long either, within a couple of years, he puts his own foundry out of business, because his number one customer is Intel products." He knows that prospective customers have been running test chips, samples and data reviews with Intel Foundry for at least two years. The absence of commitment after that much engagement is itself the datapoint on process competitiveness. What could change it, in his view, is not purely technical. Two exogenous tailwinds are now in play. TSMC leading-edge capacity is on allocation, so second-source conversations are being driven partly by desperation rather than preference. And there is a political layer around domestic capacity that he assumes is present in the shadows of these decisions. He credits Lip-Bu Tan with identifying waste and making necessary decisions into a genuinely broken situation. His objection is to method rather than direction: capable long-tenured people pushed out because the incoming CEO did not know them, replaced by people brought in from adjacent industries. He also puts the start of the decline around 2012, well before Gelsinger, and characterizes Gelsinger's plan as broadly right but poorly executed and over-committed. Conclusion: Intel is obviously far behind TSMC when it comes to process know-how and yields, but has an opportunity in the coming years to pick up volumes as TSMC is at 100% utilization. Larger volumes should lead to better yields and increase the learning curve for Intel, but obviously, this remains a difficult story. TSMC is obviously far ahead and is building additional N3 and N2 capacity to address wafer supply shortages themselves. $INTC $TSM $ASML