Sarah Chieng(@MilksandMatcha):It is interesting to see the industry move from 12Hi back toward 8Hi HBM just as DRAM stacking is accelerating. Going vertical does not make the fundamental constraints of memory disappear. As stacks get taller, thermals, power, yield, packaging, and reliability become increasingly difficult architectural problems. HBM stacks DRAM vertically beside compute. The next frontier (as seen at hot chips) is stacking DRAM directly on compute, turning the interface from the edge of a chip into its entire surface area.

Sarah Chieng

@MilksandMatcha

Head of DevX @Cerebras prev. @ExaAiLabs, @MIT wife to @tyler_fong_

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Sarah Chieng@MilksandMatcha

2026.09.01 17:44

It is interesting to see the industry move from 12Hi back toward 8Hi HBM just as DRAM stacking is accelerating. Going vertical does not make the fundamental constraints of memory disappear. As stacks get taller, thermals, power, yield, packaging, and reliability become increasingly difficult architectural problems. HBM stacks DRAM vertically beside compute. The next frontier (as seen at hot chips) is stacking DRAM directly on compute, turning the interface from the edge of a chip into its entire surface area.

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