SemiAnalysis(@SemiAnalysis_):Why did Intel abandon EMIB for their 2027 Diamond Rapids CPU? Uniform Memory Access. All CPU cores in each CBB can access all 16 memory channels with a single hop. UCIe-S through the substrate was required to route signals underneath the near-IMH to the far-IMH with about 30mm of reach to achieve this. In contrast AMD's Venice is a NUMA design. Half the memory channels are on a remote-IOD that require an extra hop for the cores in the CCD to access vs memory channels in the local-IOD. As a bonus, Intel also saves on packaging cost without having to use EMIB, freeing up advanced packaging capacity for their external foundry customers

2026.09.04 14:03

Why did Intel abandon EMIB for their 2027 Diamond Rapids CPU? Uniform Memory Access. All CPU cores in each CBB can access all 16 memory channels with a single hop. UCIe-S through the substrate was required to route signals underneath the near-IMH to the far-IMH with about 30mm of reach to achieve this. In contrast AMD's Venice is a NUMA design. Half the memory channels are on a remote-IOD that require an extra hop for the cores in the CCD to access vs memory channels in the local-IOD. As a bonus, Intel also saves on packaging cost without having to use EMIB, freeing up advanced packaging capacity for their external foundry customers

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