John Intel(@intelfabs):High‑NA EUV $INTC $ASML Intel proved it works in high‑volume manufacturing DRAM has the strongest economic reason to adopt High‑NA first Because DRAM scaling is hitting extreme patterning complexity: Very dense capacitor + bitline structures More EUV layers per generation Multi‑patterning costs exploding HBM4 and HBM5 require extremely tight pitches High‑NA reduces the number of EUV exposures and cuts multi‑patterning steps — saving cost. Samsung logic and TSMC will adopt High‑NA around A10 nodes (~2030). Intel is the High‑NA frontrunner in logic

2026.09.02 13:24

High‑NA EUV $INTC $ASML Intel proved it works in high‑volume manufacturing DRAM has the strongest economic reason to adopt High‑NA first Because DRAM scaling is hitting extreme patterning complexity: Very dense capacitor + bitline structures More EUV layers per generation Multi‑patterning costs exploding HBM4 and HBM5 require extremely tight pitches High‑NA reduces the number of EUV exposures and cuts multi‑patterning steps — saving cost. Samsung logic and TSMC will adopt High‑NA around A10 nodes (~2030). Intel is the High‑NA frontrunner in logic

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