PTI ( FOPLP ▍FOPLP (Panel-Level Packaging) vs. CoWoS With CoWoS capacity remaining tight, PTI (Powertech) isn't looking to directly displace TSMC — it is offering hyperscalers and chipmakers a cost-effective alternative via Fan-Out Panel-Level Packaging (FOPLP). ▍The Long Road to Panel PTI Chairman DK Tsai and the late Marvell co-founder Sehat Sutardja saw this coming as early as 2015–2016: flagship multi-die/chiplet architectures would eventually outgrow the physical and economic limits of 300mm round wafers due to poor edge utilization. After Sehat's departure from Marvell, PTI pushed forward on FOPLP largely on its own for years, absorbing depreciation while refining panel warpage control and RDL yields. ▍Capacity & Economics Scale: PTI has established ~6,000 panels/month capacity (510×515mm, translating to ~3x the usable area of 300mm wafers). Revenue & Margins: Traditional OSAT packaging typically commands ~20% gross margins, whereas high-end CP/FT testing reaches 30–40%. For fully utilized advanced FOPLP lines, PTI targets a high-end margin profile of ~40%.