Is $VUZI the newest micro-cap optical play? They are a smart-glasses company that have started shipping evaluation samples of an optical interconnect that can route up to 19,200 separate light paths across a distance of roughly 30mm. We know that as chips become more powerful, the electrical connections moving data around them have to run faster, which increases power consumption and heat. This is why the industry will be moving optical connections closer to the chips through architectures like NPO, CPO and eventually optical I/O. Vuzix’s approach spreads the data across thousands of light paths inside a thin waveguide. This is very early but they seem to be aggressively going after NPO and CPO. It is a pretty wild crossover, but there is a technical connection here. Vuzix has spent nearly 20 years designing waveguides and developing nanoimprint manufacturing to replicate extremely small optical structures at volume. The original application was smart glasses, while that ability to precisely route light at scale could also have a use inside AI infrastructure. This is what they claim: "As AI systems continue to scale, bandwidth is increasingly achieved through parallelism rather than speed alone. Traditional SerDes architectures push a small number of electrical lanes toward their physical limits, while waveguide-based optical architectures enable thousands of parallel channels that dramatically increase aggregate bandwidth, scalability, and energy efficiency." Will be keeping an eye on it! I just came across this news yesterday.

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Yknow as much as im doom and gloom when it comes to armored core 6's state of abandonment, i am VERY glad that the game retains the best part of any mecha game Visual customization, custom decal and photomode That and also releasing AC6 30MM Kits

Why did Intel abandon EMIB for their 2027 Diamond Rapids CPU? Uniform Memory Access. All CPU cores in each CBB can access all 16 memory channels with a single hop. UCIe-S through the substrate was required to route signals underneath the near-IMH to the far-IMH with about 30mm of reach to achieve this. In contrast AMD's Venice is a NUMA design. Half the memory channels are on a remote-IOD that require an extra hop for the cores in the CCD to access vs memory channels in the local-IOD. As a bonus, Intel also saves on packaging cost without having to use EMIB, freeing up advanced packaging capacity for their external foundry customers

Does anyone know where to find a modern S-param model for large package (30+mm trace) that includes ball capacitance and pkg core? Been using an model from 802.3ck library. Its not going well. Not sure if its cause model from 2018, made by $MRVL employee, or me stupid.