Fable 5.2 is very token inefficient for certain tasks due to its increased persistence and proclivity for spawning subagents. For example, on GDPx materials science tasks, Fable 5.2 costs 89% more than Astra and uses 4.3x more output tokens to achieve effectively the same score. The price difference vs Gemini 4 Carbon is even more startling at 7.5x. (1/3)🧵

ALERT🚨🚨: AMD MI355 is 1.42x FASTER THAN GB300 NVL72. THIS IS ACHIEVED USING THE TILERT SOFTWARE, WHICH GETS 1330 p90 tok/s/user on long context workloads! Thanks to AMD leadership for providing an MI350 cluster to TileRT maintainers, enabling them to achieve this great result!

We Visited China’s Stargate in Inner Mongolia A wind-powered 800MW campus, 120MW built within a year, a 5MW SST-native 800V DC pilot and a cooling design without central chillers

After DeepSeek V4.1 Flash, Xiaomi MiMo is moving to a causal encoder-decoder for its next-gen models. HySparse2: prompts run through only 25 of 49 layers. Decoder KV is projected from encoder states. At 1M context vs MiMo-V2: 5x less prefill compute, 4.5x smaller KV cache.

Nvidia Rubin Teardown! Direct from SemiAnalysis: in the lab, on the bench. Reach out to sales@semianalysis.com now to learn how you can get early access to the hardest hitting insights in DC/AI hardware.

The Iron(wood) Throne: Google's TPU Stakes Its Claim on Inference Viable Alternative of CUDA Moat, NVIDIA Working Nights & Weekends, Jensen’s Counter Submission, Kimi K3, Meta Muse Spark Open, GLM5.3, TorchTPU, SGLang, vLLM, llm-d, Ray

Today we’re releasing GDPx, a benchmark for measuring agentic capabilities across the most valuable domains. GDPx is a true frontier-level benchmark: even the best model scores just 12% (1/7)🧵

BREAKING NEWS🚨: HBM CHIPS CAN REACH OVER 1000 tok/s/user on giant 700B+ models via agent swarm-written software, according to a new NVIDIA AgentX submission. Furthermore, on Rubin NVL72, it can achieve 20.9x better perf per TCO than GB300 NVL72 at even "ultrafast" speeds of 325 tok/s/user and up to 9.11x better perf per TCO at 200 tok/s/user. (1/2)🧵

BREAKING NEWS🚨: NVIDIA has mainly only shown love to Blackwell Ultra & Rubin with its decode-specialized software, but has shown mostly none to the GPU Poors on Hopper or Blackwell 😭 Luckily, @mgoin_ cares about the proletarians too and got his agent swarm to write 10,000 LoC of ultra-fused Hopper kernels that improve decode speeds by up to 38%!

ALERT🚨🚨🚨: AMD's @AnushElangovan and his team have achieved up to 2x better performance per dollar than even B200 on Kimi K3 Agentic Inference! This is due to various software optimization efforts, including tuning AITER kernels and MonoKernel decode. Along with MI355X having 2304GB of HBM per server, this allows it to avoid crossing slow 8x400Gbit/s scale-out networking between servers, which B200 needs to do due to having less than 1.5TB of HBM. Great work to Anush, Peng Sun, Ramine, Emad, and the vLLM team for this amazing work!

NVIDIA has revised Vera Rubin NVL72’s NVLink bandwidth from 3.6 TB/s to 3.0 TB/s per Rubin GPU package, a ~17% reduction. Vera Rubin utilizes bidirectional SerDes, with a theoretical full-rate bandwidth of 448 Gbps per physical connection. However, crosstalk, insertion loss, and return loss create significant signal integrity challenges at these speeds. (1/2)🧵

ClassOne Solstice Max at SEMICON West ClassOne showcased its Solstice Max at SEMICON West. The 200/300mm single-wafer platform integrates electroplating, wet etch, strip and cleaning, and scales from 4 to 16 chambers. It targets advanced packaging metallization. Source: SEMICON West booth

ALERT🚨: GB300 NVL72 @sgl_project can get close to 1000 tok/s/user on DeepSeek Flash v4.1 by aggressively fusing kernels together!! TileRT started this trend in the ecosystem of megakernel engines on OSS frontier models! Glad to see SGLang widely adopting it! Great work by the SGLang, @radixark, and NVIDIA teams on pushing performance!

ASE showcased its panel-level packaging (PLP) solution for AMD’s Venice CPU, with initial production targeted for Q1 2027, likely at limited scale at its Kaohsiung facility. ASE and its subsidiary SPIL have worked with AMD to implement the second generation of their Fan-Out Embedded Bridge (FOEB) technology in Venice. The current 310 × 310 mm panel accommodates 25 Venice interposers after edge loss, compared with 22 on a traditional round 300 mm carrier wafer, roughly a 14% increase in gross package count. This modest improvement in package output per carrier represents a starting point for panel-level interposers with Venice’s 2.7x reticle size, rather than evidence of a dramatic reduction in cost. (1/2)🧵 Source: OCP ASE Booth