"Install ROCm. Make no mistakes." Tell your coding agent what you want to run. Let ROCm 10 help handle the path from intent to deployment. @AnushElangovan shows how AMD is building a more seamless, AI-native developer experience on @chain_ofthought with @ConorBronsdon. Watch the full ep:

Meet ROCm 10. Here are 10 things #AMDevs# need to know. 1️⃣ ROCm 10 brings AI-driven development to AMD platforms 2️⃣ ️ is the AI-native software experience on AMD hardware 3️⃣ delivers 3.3x inference & 2.4x training improvement vs. ROCm 7 on the same hardware 4️⃣ ROCm Core SDK is open-source and optimized for AI workloads so you can customize the stack for your workload needs 5️⃣ ROCm 10 ships production-ready support for @vllm_project and @sgl_project 6️⃣ ROCm Hyperloom optimizes end-to-end inference 7️⃣ Run ROCm Hyperloom standalone or through AMD Skills 8️⃣ AMD Skills provide software and hardware expertise for your coding assistants 9️⃣ AMD Skills support the coding assistants you already use 🔟 10 years. And we're just getting started! Introducing the AI-native evolution of the developer platform for AMD hardware:

Training and rollout logprobs matched bit for bit on ROCm. The @RLKernel team integrated RL-Align/RL-Kernel with vllm-project/vime. A 200-step Qwen3-8B GRPO run on 8× @AMD MI300X recorded zero logprob mismatches between Megatron training and vLLM rollout. The strict path aligns reduction order, intermediate precision, rounding points, and math primitives across both sides. Deep dive:

Get started with Muse Spark Open: NVIDIA: vllm/vllm-openai:muse-spark-open AMD: vllm/vllm-openai-rocm:muse-spark-open Recipe: Model: Technical deep dive: Thanks to everyone involved for the great collaboration! 🤝 6/6

Massive shoutout to TJ & Team at @EmbeddedLLM; they are the lead maintainers & CODEOWNERS of vLLM ROCm! Up until May 2026, they did not even have persistent access to an MI355X cluster, but after SemiAnalysis worked with & convinced AMD leadership of something that is quite obvious in hindsight, they finally got a persistent cluster to make MI355X great on AMD! Super proud of the @EmbeddedLLM Team, highly respected within the @vllm_project community.

New on the PyTorch Foundation blog: @AMD and @Meta contributors share how PyTorch Monarch was brought to AMD Instinct GPUs with ROCm to support fault tolerant distributed training at scale. The post walks through the ROCm port of Monarch’s GPU runtime and distributed communication stack, then shows how Monarch, TorchFT, and TorchTitan enable healthy replicas to continue training while failed nodes recover and rejoin without a full checkpoint restart. Validation includes Llama 3 8B training on a 128 GPU AMD Instinct MI300 SLURM cluster and a 256 GPU AMD Instinct MI355 Kubernetes cluster. Read the full technical deep dive:

At OCP Global Summit 2026, @AMD's Director of Business Development Ted Marena gives a sneak peek into Supermicro MI350P systems and AMD ROCm software. Uncover how Supermicro and AMD give enterprises a practical way to deploy AI in existing data centers: #Supermicro# #AMD# #ROCm# #AI#

The AMD AI DevDay World Tour is coming to a city near you! 🌎🌍🌏 Join us for a day of AI development, workload optimization, and ROCm certification. Check out the DevDay locations:

Today, we are announcing an engineering collaboration with @AMD to strengthen production agentic inference on AMD Instinct GPUs in @vllm_project. AMD brings the Instinct platform, ROCm engineering, and the AITER kernel library, while Inferact and the vLLM community bring model integration, serving features, and day-0 enablement. Together, we are focused on agentic workloads with long-running sessions, long prefixes, and tool calling, and each configuration will ship as a public per-model serving recipe. This work is already running in production. It shipped with this summer’s major open-model releases, and Inferact uses it on AMD Instinct clusters for our Inferact Platform customers. Everything this collaboration produces lands in open source. Read the full announcement:

The hardware work reaches across the serving stack. NVIDIA's FlashInfer and vLLM optimizations include fused norm/gating/residual kernels, TEP pooler/unpooler sharding with fused MNNVL collectives, and an FP32-norm-to-TF32-router path. AMD MI355X supports FP8 and MXFP4 with TP/PP on ROCm. Initial TPU support uses TorchTPU. With DSpark (acceptance length = 6), Muse Spark Open megakernels reach over 650 tokens/sec on 4 TPU v7 chips and 960 tokens/sec on 8 chips; without speculation, over 270 and 350 tokens/sec. Code access is available through the team or Google. 4/6