People always ask: where's the next structural opportunity in AI chips? One of the structural shifts driven by the paradigm change over the past few months is heterogeneous AI inference — and SRAM-route startups led by Cerebras is right at the frontier of this new trend. Every year, Nvidia's GTC conference introduces paradigm-shifting concepts in technology, setting the benchmark for the entire industry. Everyone scrambles to rewrite their roadmaps and copy the homework after GTC. ------------------------ To understand where SRAM-route companies fit in the ecosystem, you first need to look at the workload characteristics of different stages of genAI inference. It breaks down into three parts: Prefill: extremely high compute intensity, low demand on memory bandwidth, moderate-to-high demand on memory size. Decode-stage attention: moderate compute intensity, extremely high demand on memory bandwidth (repeated reads/writes to KV cache), extremely high demand on memory size, because KV cache grows linearly as batch size increases. Decode-stage FFN: moderate compute intensity, extremely high demand on memory bandwidth (repeated reads of model weights), moderate-to-high demand on memory size (model weights). The characteristics of SRAM-route chips are equally clear: They push memory bandwidth to the absolute extreme, but everything else is a severe weakness. They fundamentally trade off compute intensity and the inability to scale memory size for the ultimate in memory bandwidth speed. --------------------- Now let's look at SRAM's suitability across the three stages of AI inference: Prefill: SRAM can't achieve high compute intensity because SRAM takes up too much die area, leaving limited space for compute units. So prefill is a weak point. Decode-stage attention: SRAM can meet the high memory bandwidth requirement, but its memory size is too small to handle the batch size demands. So SRAM only satisfies half the requirements for attention. Decode-stage FFN: SRAM can meet the high memory bandwidth requirement, and the memory size requirement is moderate. Through optimized interconnect communication, SRAM chips can barely solve the memory size problem — the cost is steep, but the ROI can still pencil out in certain scenarios. ---------- So the applicable scope of SRAM-route accelerators in heterogeneous AI inference is crystal clear: Prefill — forget about it. Garbage performance, garbage economics. Decode-stage FFN — with enough effort and added cost, it's within reach. Decode-stage attention — KV cache demands on memory size are too extreme, and the cost of batch processing is prohibitively high. Letting Cerebras's $2.3 million-per-chip, 45-chip, $100-million luxury system serve as an exclusive ultra-VIP service — sure, that technically works. Imagine this: one or two users running agent flow on a coding task with 1–2M context length, and it takes the entire 44GB of SRAM on a single $2.3M Cerebras chip just for KV cache, otherwise the speed tanks. What kind of extravagant service is that? ------------- So the conclusion couldn't be more obvious: if Cerebras tries to do full-stack AI inference on its own (prefill + decode ATTN + decode FFN), the economics simply don't work. There's no future in it. Because the cost of Cerebras is staggering. Even with their gross margins squeezed razor-thin, the implied rental rate of each CS-3 system is still $41.96/hour — roughly ten times the rental of a B200. And that's for a single CS-3. You need to chain many of them together for LLM inference, so multiply that rental by a lot more. This is precisely why the economics of the SRAM route are so poor — Nvidia already made this point crystal clear at GTC (see chart). People hyping up SRAM as the future replacement for HBM? That's a pipe dream. With SRAM scaling already hitting a wall, SRAM density per generation of chips is already nearly impossible to improve. On the memory size dimension, HBM's exponential growth will only widen the gap with SRAM further. Even on the memory bandwidth dimension, HBM is growing exponentially too, narrowing the gap with SRAM. So Nvidia's solution is elegant and clean: hand off the decode-stage FFN to the SRAM route, keep everything else on traditional HBM GPUs, and push the entire Pareto frontier significantly toward the upper right. Rubin + LPX breaks through 1000 tokens/s at peak speed while still maintaining enough overall throughput to generate real commercial value (this is critically important). Remember — on Blackwell, if you wanted to hit 400–500 tokens/s at high speed, you could only process a tiny handful of concurrent requests. That's a massive waste of GPU resources. But now, even at 1000 tokens/s, you can still maintain a meaningful batch size (throughput), and it can finally generate commercial value. The chart shows that at 400 tokens/s, Rubin + LPX delivers a 35x improvement in throughput — classic token economics. At that token speed, it represents a 35x improvement in commercial value over Blackwell. --------------------- After GTC revealed this standard answer — and even earlier, after the Groq LPU acquisition — everyone has already started copying this homework on the heterogeneous inference front. Google's TPU tapped Marvell for the SRAM component. Amazon AWS's Trainium tapped Cerebras for the SRAM component. ByteDance's AI ASIC tapped Qualcomm for the SRAM component. We will absolutely see more announcements like these in the future. And this is the best path to economic sustainability for Cerebras: stop trying to muscle through full-stack AI inference, focus on what you're good at, partner with mainstream AI ASICs on inference, and fight to embed your SRAM chips into other companies' decode FFN pipelines. This is also why the key to Cerebras's long-term trajectory hinges on how deeply it can integrate with AWS Trainium's disaggregated inference. If it's just what's been reported so far — Trainium handles prefill and Cerebras handles decode as a simple split — the technical implementation difficulty is much lower, but the economics still don't pencil out. It can only be a strategic positioning play — enough for a slice of the market, but not enough to generate real scaled competitive advantage. To follow the Nvidia playbook, they need deep integration of both companies' strengths — and that will take real time and technical effort, with non-trivial difficulty, but the payoff would be worth it. Solution one: Trainium handles prefill and decode attention, Cerebras handles decode FFN. Solution two: Cerebras runs the draft model, Trainium runs verification. Either solution delivers dramatically more market competitiveness. -------------------- Does this kind of partnership with mainstream AI ASICs shrink the TAM for SRAM-route companies? No. This is the only long-term sustainable path for SRAM-route companies to grow their market. Heterogeneous AI inference is unequivocally the future. Finding your piece of the puzzle early in this growing blueprint is the only way to grow alongside the market. The moment an SRAM-route company embeds itself into any mainstream AI ASIC's heterogeneous inference pipeline, its valuation will skyrocket — because the TAM in terms of unit shipments isn't even in the same order of magnitude. Otherwise, heterogeneous AI inference will relentlessly erode the speed advantage of the SRAM route on the token speed dimension (not throughput). Full-stack inference on the SRAM route degenerating into an expensive toy is an inevitable outcome.

AI Semiconductor Endgame 2026 (Part 1) New Token Economics Computing Paradigm Shifts from GPU Compute to HBM This article starts from the essence of GPU architectural evolution to address a question the market has long worried about: Why must each GPU's HBM memory demand grow exponentially, and why won't this exponential growth in HBM demand stall? It then derives the first principle of token economics under the current architecture: token throughput = HBM size × HBM BW (bandwidth) It also discusses why the GPU ceiling is determined by HBM's two dimensions of progress. The topic of HBM cyclicality has long been controversial. Optimists argue that AI-driven demand is much greater than before, but the market mainstream still believes that previous up-cycles also saw 20%+ annual demand growth — so what's different this time? AI doesn't change the fact that HBM, like traditional DRAM, has commodity attributes. Once capacity expansion at the demand peak meets a downturn, history will repeat itself. We can take the perspective of compute-chip architecture, start from first principles, and unpack and reason through this question: why this time is genuinely different. ——————————————————————————————— History: The Era of CPU Compute For a very long time, we lived in the era of CPU-dominated compute. The CPU's top-level KPI was performance — running faster — and so each generation of CPUs deployed every method imaginable to push benchmark scores higher. First it was rising clock frequencies, then it was architectural evolution: superscalar designs, and so on. During this period, why didn't DDR need to advance technologically at high speed? DDR3 to DDR5 took a full 15 years. Because in this era, DDR's role was purely auxiliary — and only weakly so. By industry experience, even doubling DDR speed would generally only raise CPU performance by less than 20%. Why did improvements in DDR bandwidth and speed matter so little? Two reasons: 1. CPUs designed all kinds of architectural tricks to hide DDR latency — superscalar designs, wider issue widths, massive ROBs and register renaming to extract parallelism and hide latency, L1 caches, L2 caches — all of which weakened the demand for DDR bandwidth and speed. 2. CPU workloads don't have particularly demanding bandwidth requirements. For most everyday workloads — say, opening a webpage — DDR bandwidth is severely overprovisioned. Even cloud workloads often look the same. In other words, in the CPU era, DDR bandwidth and speed didn't really matter. There was virtually no difference between DDR4 and DDR5 except in a handful of games — and even the JEDEC standard advanced slowly. On top of that, only a small portion of any given app needs to permanently sit in DDR. Whatever is needed can be paged in from the hard drive on demand. App size grew slowly, and so DDR capacity demand grew slowly as well. That's why, over the past decade, the average PC went from 7–8GB of DDR to about 23GB — only 3× growth in ten years. This slow upgrade pace directly affected revenue. Capacity-based pricing was the main way of making money; speed improvements were just a technological upgrade that raised the unit price of capacity. With both of these dimensions advancing slowly, growth could only come from increases in PC/phone unit volumes. So along both dimensions — bandwidth/speed and capacity — DRAM was always a “nice-to-have” appendage to the chip industry. The marginal utility of DDR upgrades was very low, and almost completely disconnected from the CPU era's top-level KPI. ——————————————————————————————— The Paradigm Shift: GenAI's Top-Level KPI When we entered the era of GenAI large models, the computing paradigm shifted, and the top-level KPI changed fundamentally. By the time GPUs evolved into AI inference engines, the top-level KPI was no longer compute alone (TOPS/FLOPS), as it had been for CPUs — it became the cost of a token. Specifically: overall token throughput per unit cost / per unit power. A close second is token throughput speed — because in the agent era, many tasks have become serial, and token output speed has become a critical bottleneck for user experience. This is exactly why Jensen invented the concept of the AI factory: to produce the most tokens at the lowest cost, while pushing token throughput speed as high as possible. In the AI training era, Jensen's economics were TCO (Total Cost of Ownership): the more GPUs you buy, the more you save. In the inference era, Jensen's token economics flip the logic: AI inference has very healthy gross margins, so the logic now becomes: the NVIDIA GPU is the GPU that produces the cheapest token in the world, so the more you buy, the more you earn. The top-level KPI has become a Pareto frontier: along the two dimensions of token throughput and token speed, optimize as far as possible. Each generation of NVIDIA's token factory is essentially pushing the entire Pareto frontier up and to the right. This is the most important KPI of the AI inference era. ——————————————————————————————— From Token Throughput to HBM: The Core Logic Chain Below is the most important logical chain of this article: how to start from the exponential growth of token throughput and derive that the ceiling bottleneck lies in the exponential growth of HBM size and HBM speed. In the era of single-GPU inference with single-thread batch size = 1, token throughput had only one dimension: HBM bandwidth speed. Higher bandwidth = higher token throughput. But once we entered the NVL72 era, inference is no longer single-GPU. It is a system-level token factory composed of 72 GPUs + 36 CPUs, designed to fully saturate HBM bandwidth and compute simultaneously, in pursuit of the ultimate token throughput. Token throughput growth depends on two things: the number of requests batched simultaneously × the average token speed per request. That is: batch size × token speed. Take Rubin NVL72 as an example. At an average token speed of 100 tokens/s, processing 1,920 simultaneous requests yields a token throughput of 192,000 tokens/s. A Rubin NVL72 draws roughly 120kW (0.12MW), so per MW it can handle 1.6M tokens/s. So we need to find ways to push both parameters up: batch size and average token speed. Their product is our top-level KPI — token throughput. Parameter 1: Batch growth — bottleneck is HBM size Every request in the batch carries its own KV cache, which has to live in HBM, with sizes ranging from a few GB to tens of GB. Because hot KV cache must be read at high frequency and high speed at any moment, it must reside in HBM. For a model with, say, 80 layers, every token generation step requires reading the KV cache 80 times from HBM. As batch size grows, hot KV cache grows linearly. And because the hot KV cache for every request in the batch must sit in HBM, HBM size must grow linearly with batch size. Like an airport shuttle bus: the gate wants to move passengers to the plane as fast as possible. If HBM size is small, the shuttle is small, so you have to make extra trips. Conclusion: batch size growth bottlenecks on HBM size growth. Parameter 2: Average token speed per request — bottleneck is HBM bandwidth The decode-phase speed of a large model bottlenecks on HBM bandwidth, because every token generated requires reading the activated weights and KV cache many times over. The emergence of LPUs has, in cases where batch size isn't very large, moved the activated weights portion onto SRAM — but every generated token still requires many reads of the KV cache from HBM. The higher the HBM bandwidth, the faster each token is generated, in essentially linear correspondence. Like the airport shuttle bus: HBM bandwidth is like the width of the door — wider doors mean passengers board faster. The rest of the GPU's configuration is essentially adapted to support batch growth and to keep token compute speed in step with HBM growth. In some cases the GPU even spends excess compute to recover effective bandwidth (e.g., bandwidth compression techniques). —------- To return to the shuttle bus analogy: • Shuttle bus cabin size = HBM Size (capacity): determines how many passengers can fit at once (i.e., how many requests' KV caches can sit in HBM simultaneously). Bigger cabin = more passengers (higher batch size) per trip. If the bus is too small, moving 100 people takes two trips — and total throughput suffers. • Shuttle bus door width = HBM Bandwidth: determines how fast passengers get on and off. A wide door, and everyone piles on at once (decode/token generation is fast). A narrow door, and even with a giant cabin, people queue up and most of the time is spent boarding. • Passenger throughput = cabin size × door-width-determined boarding speed. —------- At this point, we've logically derived the first principle of token-economics hardware demand: Token throughput = HBM size × HBM Bandwidth The top-level KPI of the AI inference era is highly dependent on progress along both HBM dimensions. If we want to maintain 2× token throughput growth per generation, that means each generation of single GPU must grow HBM size × HBM BW speed by 2×! This is the first time in history that HBM memory size can influence the top-level KPI — token throughput. To validate this thesis, we can put NVIDIA's token throughput from A100 to Rubin Ultra on the same chart as HBM size × HBM BW speed. What you find is that the two curves track each other startlingly closely on log axes. HBM size × speed actually grows even faster than token throughput — which makes sense, because HBM defines the ceiling, and in practice utilization of that ceiling is very hard to push to 100%. Even if HBM size × HBM speed grew by 1,000×, with the supporting compute and architecture, it would be very hard to wring out the full 1,000× of headroom. This curve isn't a coincidence — it's the necessary solution of system optimization. throughput = batch × speed. This is the unavoidable first principle of token factory economics. —------- What about software? Won't software optimization reduce bandwidth demand? Reduce HBM demand? This is an independent dimension from hardware. It's like asking: if software on a CPU runs faster after optimization, does that mean the CPU doesn't need to advance for ten years? After all, software is faster now. If that were the case, would CPU vendors still make money? For a CPU vendor to survive, there's only one path: in standardized benchmarks, ignoring software optimization, every new CPU generation must score higher — otherwise it doesn't sell. GPUs are exactly the same. How well software is optimized, and the requirement that the GPU's own token-throughput KPI must improve dramatically every year, are two separate things. As long as token demand keeps growing, the pursuit of higher token throughput will not stop — and so neither will the pursuit of higher HBM size × HBM speed. If HBM size and HBM speed were to slow down, Jensen would personally fly to the Big Three and pressure them to accelerate, because that ishis GPU ceiling. If the ceiling stops rising, can his GPU still sell? Of course, NVIDIA also needs to wrack its brains to extract performance beyond the HBM ceiling through heterogeneous architectural angles. The LPU is a great example — it improved the Pareto frontier substantially from a different angle (the right-hand high-token-speed portion). —-------------------- HBM memory has now bid farewell to that old era of drifting with the tide. On this one-way road paved by exponential demand, it has, in something close to a destined fashion, walked onto the central stage of the industry's epic. When the inference paradigm's first principles evolve to this point, as long as Jensen still wants to sell GPUs, HBM must double — and it must double every generation. This is endogenous pressure from the supply side. It has nothing to do with AI demand, nothing to do with macro cycles, and nothing to do with the moods of the hyperscalers. The only remaining question is this: When demand has been physically locked into exponential growth, will the three players on the supply side — like they have for the past thirty years — once again drag themselves back into the mire of the cycle by their own hands?