aog T(@Taog_1575):Because the video is formally rls so we can use the picture 1 XD And the decap team told me their A20 Pro decap results may have some magnitude error on the FIB/SEM image. And this time, they change the FIB lab for D9600/ 8EE6 decap, and actually they are the most closest one to the real dimension so far. Below we list the N2 dimension number from different sources: HD cell G48H130, 236.17mtr (SNPS, N2P) G47H125, 250.84mtr (TI, A20 Pro, N2) G47H127, 246.89mtr (D9600&8EE6, N2P) HP cell G48H156, 196.81mtr (SNPS, N2P) G47H150, 209.03mtr (TI, A20 Pro, N2) G47H152.5, 205.61mtr (D9600/8EE6, N2P) ———————- You may be confused for above dimension results, but remember the dimension obtained from decaping may have some image error. And previously, I have said 18A density (cell level) is 33-34% inferior to N2, and you can not obtained this value from SNPS’s data (G50H160 vs G48H130). This is because SNPS sometimes will not update the optical shrink, like N4 still be labeled as G51H210, the same as N5, but we know it has 2% optical shrink and yield in 4% density gain. Remembered, TSMC has stated that N2 and N2P have no density difference, so you should know what happen and how to interpret the above decaping dimension XD And finally, I use the precise dimension to plot the cell level density chart for different node (calculated from real dimension, not from decap results). PS1. We use cell level density, not block level density to simplify the comparison: https://t.co/q0J5DPmtTv PS2. 14A2 is bring by Wei Jan so you could see there has an optical shrink on 2031 XD 14A truely reduce the density gap from 18A >30% to 20-30% level. But that is logic. If we also consider the SRAM bitcell area gap, then the total gap will not reduce from N2 vs 18A XD (remember 18A SRAM bitcell area is tha same as N2).

2026.10.27 23:29

Because the video is formally rls so we can use the picture 1 XD And the decap team told me their A20 Pro decap results may have some magnitude error on the FIB/SEM image. And this time, they change the FIB lab for D9600/ 8EE6 decap, and actually they are the most closest one to the real dimension so far. Below we list the N2 dimension number from different sources: HD cell G48H130, 236.17mtr (SNPS, N2P) G47H125, 250.84mtr (TI, A20 Pro, N2) G47H127, 246.89mtr (D9600&8EE6, N2P) HP cell G48H156, 196.81mtr (SNPS, N2P) G47H150, 209.03mtr (TI, A20 Pro, N2) G47H152.5, 205.61mtr (D9600/8EE6, N2P) ———————- You may be confused for above dimension results, but remember the dimension obtained from decaping may have some image error. And previously, I have said 18A density (cell level) is 33-34% inferior to N2, and you can not obtained this value from SNPS’s data (G50H160 vs G48H130). This is because SNPS sometimes will not update the optical shrink, like N4 still be labeled as G51H210, the same as N5, but we know it has 2% optical shrink and yield in 4% density gain. Remembered, TSMC has stated that N2 and N2P have no density difference, so you should know what happen and how to interpret the above decaping dimension XD And finally, I use the precise dimension to plot the cell level density chart for different node (calculated from real dimension, not from decap results). PS1. We use cell level density, not block level density to simplify the comparison: PS2. 14A2 is bring by Wei Jan so you could see there has an optical shrink on 2031 XD 14A truely reduce the density gap from 18A >30% to 20-30% level. But that is logic. If we also consider the SRAM bitcell area gap, then the total gap will not reduce from N2 vs 18A XD (remember 18A SRAM bitcell area is tha same as N2).

aog T@Taog_1575

2026.10.26 15:50

This is a good example why I continued to use cell level density but not block level density. Because when you want to use block level density compared different node, especially cross foundry comparison, too many detail you need to be considered. Like 18A vs N2 case, some people may say 18A has BSPDN so you should considered the block level density gain by BSPDN. Yes, because BSPDN move some metal layer to backside, so some dummy metal can also be placed and shared the backside space, so your device metal routine resource increase and block density may gain in some case. Actually, this block level density gain number by BSPDN is floating. Some case especially you use larger amount of HP/ UHP cell with dense power grid, this number can enlarge to ~20%. But in most case, a ~10% gain in area will be mentioned and estimated. However, if you want to compared the block level density, then many design rule detailed and DTCO you must considered. Like N2 offer NanoFlex that providing short-tall cell abutment that could yield in 15% performance gain under same area or translate to x% area gain under same performance, and 18A do not offer this DTCO until 14A. So how do you compared these block level density gain? Dummy rule constrained or dummy area reduction is another example, like Xiaomi claim 5% block level density gain by scrub line area reduction with O3 chip compared to O1 chip. So how can you confirm to add these extra 10% block level density gain by BSPDN on 18A but not considered the DTCO area gain on N2? Hence this ~10% density gain is only suit for same foundry comparison with FSPDN vs BSPDN in some applications. ( andto be mentioned, HD cell gain from BSPDN is much smaller than HP cell). So this is why I only use cell level density to compared the different node.