Abstracts of MPS (MPWR) Note • Initiate Buy | TP $1,706
• Key position in AI power (GPU + ASIC) on Strong demand + VPD module uplift + firm pricing from DrMOS shortages
• Storage / enterprise data / auto design wins → broad recovery
• EPS forecast: $28 (2026E) / $49 (2027E)
• Target based on 35x 2027E P/E • GPU power surging (H100 → B200 → Rubin) + higher density per rack
• Conventional power delivery hits limits → strong demand for high-phase PoL VRMs (12V→1V)
• AI 12V-1V power TAM set for strong growth amid tight supply
• Differentiated tech: leading BCD process + Intelli-Phase + DPPM architectures
• Enterprise Data sales expected +153% / +81% YoY in 2026E/2027E • Long-term capacity target lifted well above $6bn
• New product ramps unlocking SAM in storage, communications & automotive
• Initial high-speed DDR5 orders secured
• Sampling high-voltage AC-DC for 800V data-center architectures
• Automotive: >1,500 new sockets shipped YTD (ADAS + in-vehicle electronics) #MPS# #MPWR#

$INTC (Bloomberg) -- Intel Corp. raised $20 billion in an upsized share sale, a third more than it was targeting when it announced the deal Monday morning. The chipmaker priced the offering at $95 per share, according to a company statement. That represents a discount of 6.5% to Friday’s closing price, according to Bloomberg calculations. The share sale drew more than $100 billion in demand, people familiar with the matter said.  Read More: Intel to Sell $15 Billion in Stock After AI Boosts Demand Intel’s deal shows the resilience of investor demand for stocks along the artificial intelligence supply chain. The year’s biggest US equity offerings have been dominated by companies riding the boom in AI spending. Alphabet Inc. is in the process of raising as much as $85 billion through equity offerings, including so-called at-the-market share sales and equity-linked deals. And Oracle Corp.’s fundraising plans include a $20 billion at-the-market sale.  Watch: Breaking Down the Billions in Nvidia Deal, Intel Sale South Korean memory chipmaker SK Hynix Inc. raised $26.5 billion in its debut offering of American depositary receipts, the largest-ever listing by a foreign company on a US exchange. Its rival CXMT Corp. raised about $9.9 billion last month in a near Chinese record initial public offering and subsequently became the largest mainland-listed company. Intel’s shares fell 1% before the market opened in New York on Tuesday, after Monday’s close of $97.52. They remain up roughly 164% this year, after Chief Executive Officer Lip-Bu Tan made cleaning up Intel’s finances a priority. The effort has included attracting outside investments from the US government and even chip rivals such as Nvidia Corp.  Intel is building up cash reserves with a goal of taking on a more central role in the artificial intelligence boom. The worldwide expansion of data centers has already bolstered demand for its general processors, but the company has struggled to compete directly with Nvidia and Advanced Micro Devices Inc. in the market for AI processors. Intel also needs funds to build out a factory network to meet its goal of serving as an outsourced manufacturing hub for the tech industry.  JPMorgan Chase & Co., Goldman Sachs Group Inc., Morgan Stanleyand Citigroup Inc. are working on the offering, according to a statement earlier. (Updates with shares in fifth paragraph.)

Interesting facts I learned today Pluggables actually use much more InP than CPO. The reason the InP trade was always associated with CPO is that the laser quality and stability is so high it’s like a double bottleneck where a small % of them can get qualified for use thus it greatly multiplies the demand for InP more than normal. Thus I see this “shortage” as extremely levered to CPO working despite having less InP content. I’m not bullish on CPO or NPO for scale up at all and even when it comes to switches and I don’t think those will be widespread for another 3 years at best. Even worst CPO is actually WORST than copper for scale up when it comes to power efficiency because of thermal tuning !!! I found this to be really shocking since that was the only real reason to use it for scale up in the first place. VCSELs seem more promising and don’t have any InP content at all. It’s too early to say if they win as there are many drawbacks but much easier to fix than CPO imo. Then we have the added fact that better chip packaging lowers pressure on networking (or at least keeps it the same) and the added fact that for inference architectures you probably can get away with just a simple 25G interconnect since bandwidth isn’t stressed as much as training. With all this being said, why would you be long the InP supply chain directly or indirectly? Seems like a lot of assumptions baked in that are going to need to become reality fast.

$AVGO Taiwan’s ODM ecosystem is becoming a critical backbone of open AI networking. Broadcom highlights local partners supporting Tomahawk 5/6 and Jericho 4 platforms, including Alpha Networks, Accton, Delta, QCT, UfiSpace, Wistron, and WNC. Taiwan’s role is expanding from manufacturing into core AI infrastructure integration.

Exclusive: SK hynix to Increase NAND Production in China by 50% SK hynix is resuming construction of its second NAND flash plant in Dalian, China, expanding its local production capacity by approximately 50%. Construction of the Dalian Fab 2 began four years ago but was suspended for an extended period following the memory market downturn. SK hynix plans to begin installing semiconductor production equipment by year-end and bring the fab into full operation in the first half of next year. According to semiconductor industry sources on August 11, Solidigm, the NAND subsidiary of SK hynix, resumed investment in Dalian Fab 2 in the first half of this year and restarted construction. Production equipment is expected to begin moving in as early as November, with the fab slated to establish a mass-production system and begin manufacturing NAND flash in the first half of next year. The new line is reportedly designed for monthly wafer input capacity of around 50,000 wafers. Combined with the existing Dalian Fab 1’s capacity of 100,000 wafers per month, this would increase SK hynix’s local production capacity by approximately 50%. Investment in Dalian is moving forward again after a four-year hiatus as the expansion of artificial intelligence data centers drives a surge in demand for enterprise solid-state drives, pushing NAND prices to nearly 10 times their level a year earlier. SK hynix launched Solidigm after acquiring Intel’s NAND business in 2021, taking over Dalian Fab 1 and the surrounding site before beginning construction of Fab 2 in May of the following year. However, the memory downturn and U.S. restrictions on exports of semiconductor manufacturing equipment to China brought progress to a halt, leaving only the fab’s structural framework completed. With the construction of Dalian Fab 2, SK hynix is pursuing a two-track NAND production and sales strategy. The company plans to manufacture lower-layer NAND based on mature technology in Dalian while concentrating production of advanced, high-layer-count NAND in Cheongju. Dalian is expected to focus on improving productivity for 100-layer-class NAND based on Intel’s mature floating-gate architecture, while production of NAND with more than 300 layers is expected to be concentrated at domestic facilities such as the M17 fab in Cheongju. The company previously announced that it would invest KRW 19.1 trillion in the Cheongju M17 fab, with plans to open its first cleanroom by the end of 2028 and manufacture next-generation NAND products there. “Dalian Fab 2 is planned to use the same equipment configuration as Fab 1,” an industry source said. “My understanding is that it will have monthly wafer input capacity of between 40,000 and 60,000 wafers.”

Samsung Electronics to Adopt High-NA EUV Technology Starting at 1nm Samsung Electronics plans to introduce a major innovation in lithography technology beginning with its 1-nanometer process, which could enter mass production as early as 2030. The company intends to deploy High-NA EUV, a next-generation extreme ultraviolet lithography technology, in volume production at the 1nm node and is currently focused on developing the technology required for commercialization. Park Chang-min, a Master at Samsung Electronics, disclosed the company’s lithography technology roadmap on August 11 at the 2026 Next-Generation Lithography + Patterning Conference (NGL 2026), held at the Suwon Convention Center in Gyeonggi Province. Lithography is the process of transferring circuit patterns onto semiconductor wafers. Samsung Electronics has used EUV lithography in volume production since introducing it at advanced foundry nodes of 8nm and below. EUV has a wavelength of 13.5nm, approximately one-thirteenth that of argon fluoride (ArF), the conventional light source used in semiconductor lithography. This allows ultrafine patterns that require multiple exposures, or multi-patterning, with ArF to be produced with fewer exposures—or even a single exposure. Reducing the number of patterning steps can lower manufacturing costs and improve productivity. Samsung Electronics is also intensifying its development of High-NA EUV, the next generation of EUV technology. The company is targeting the 1nm, or A10, process for its full-scale deployment in volume production. The “A” refers to angstroms, with one angstrom equal to 0.1nm. “We had hoped to apply High-NA EUV to volume production at the 2nm and 1.4nm nodes, but the technology still requires further refinement,” Park said. “We believe High-NA EUV will become necessary from A10 and below, and we are jointly developing the technology with various partners.” Based on this roadmap, Samsung Electronics is expected to begin using High-NA EUV in mass production around 2030. The company has already commercialized its 2nm process and plans to begin volume production of its 1.4nm SF1.4 process in 2029. It is reportedly preparing to start mass production of SF1.4+, an enhanced version of the 1.4nm process, as well as its 1nm process in 2030. High-NA EUV increases the numerical aperture, or NA, of the optical system from the current 0.33 to 0.55. Numerical aperture measures an optical system’s ability to collect and focus light. A higher NA improves resolution, making it easier to create finer circuit patterns. High-NA EUV can enable single-patterning for ultrafine features that would otherwise require multi-patterning with conventional EUV. This can improve cost efficiency. Because the pattern can be created in a single exposure, it also provides greater flexibility in circuit design. However, High-NA EUV is extremely technically challenging, and the equipment is highly expensive. Related technologies and materials, including masks and pellicles, must also advance. The industry therefore expects EUV multi-patterning and High-NA EUV single-patterning to be used in parallel at future process nodes. “Multi-patterning based on 0.33-NA EUV will remain the mainstream approach through the 1.4nm and 1nm nodes,” Park said. “For the process generations that follow, I believe High-NA patterning will become the mainstream.” $ASML

NPO presents an interim solution under the transition from pluggable to true CPO. NPO has certain benefits over CPO that bypass current production and reliability challenge of CPO, while maintaining most of the benefits CPO provide. Pros: 🟠 Better serviceability (field replacable) 🟠 Lower blast radius (blast radius limited to the individual NPO module) 🟠 Easier assembly (Optical Engine are packaged separately from the Switch ASIC/XPU) Let's look at how NPO differentiate from CPO architecturally. (1/3)🧵

The Low-DK Fabric Roadmap for AI Hardware (Gen 1 to Gen 4): • Gen 1 (Glass): NV Compute Tray • Gen 2 (Glass): NV Switch Tray • Gen 2.5 (Extreme Glass / NEZ-Grade): The physical limit of glass fiber • Gen 3 (1st Gen Quartz / Q-Glass): NV Next-Gen LPU (52-layer) • Gen 4 (2nd Gen Quartz): M10-grade CCL Gen 1–2.5 push traditional glass to its limit. Gen 3–4 leap into pure Quartz for the AI race. ⚡️ #PCB# #CCL# #NVIDIA# #Hardware# #SupplyChain# #QGlass#

BofA: Nvidia's $500B Financing > NVDA Underwrites Value, Not Debt: NVDA has signed Memorandums of Understanding (MOUs) with six top financiers (Apollo, BlackRock, Blackstone, Brookfield, Goldman Sachs, and KKR) to mobilize over $500 billion in third-party capital via independent platforms. The financial burden sits with the consortium rather than NVDA's balance sheet. > GPUs as an Investable Asset Class: With $500 billion of capital treating compute as an investable asset class, residual values must hold. NVDA supplies fungible and transferable compute across operators, and CUDA extends its useful life to keep resell/rental rates high and depreciation curves benign. > Extending the AI Buildout Runway: Funding—rather than demand—has been the primary bottleneck. A $500 billion pool allows non-investment-grade buyers (such as labs, neoclouds, and sovereigns) to secure hardware at attractive rates, de-risking offtake and supporting long-term AI systems Total Addressable Market (TAM) paths. > Key Debates and Risks Monitored: Notable cautions remain, including the fact that MOUs are not deployed capital (requiring real end-customers paying real money), potential power and regulatory pushback, input-cost inflation, and the opacity/complexity that new financing structures might introduce to AI buildouts.

The Information：微软正计划在明年大幅提升其内部设计的下一代人工智能芯片的产量，以期说服像 Anthropic 这样的大型云客户采用。 微软计划在九月发布其下一代 Maia 300 人工智能芯片 已在与芯片制造商台积电洽谈，以确保超过 30 万颗芯片的制造产能，目标是在 2027 年交付——这一数量级远超微软迄今生产的数万颗 Maia 200 芯片。 微软最终希望确保超过一百万颗 Maia 300 芯片的产能，但可能会受到组件供应以及其与台积电正在进行的产能谈判的限制。

UBS bullish on PCB/CCL: Q-glass is currently on hold after failed sampling, while an M9/PTFE hybrid has emerged as the more feasible solution - potentially reshuffling winners across the PCB/CCL supply chain. Meanwhile, 800G/1.6T optical modules and custom ASICs are becoming important nearterm PCB drivers, reducing dependence on Nvidia alone. UBS therefore sees the recent weakness as more of a reset than the end of the AI PCB cycle.

UBS on $MU: "now model MU HBM ASP up ~72% Y/Y (vs. +61% Y/Y prior) along with broadly unchanged MU HBM bit shipments of ~11.65B Gb for C2027. This comes despite changes to $NVDA Rubin Ultra specs, where our checks suggest a first VR300 variant is expected to use 384GB of HBM4 per GPU (8-Hi × 24Gb × 8 × 2 dies), with a subsequent version moving to 512GB of HBM4E per GPU (8-Hi × 32Gb × 8 × 2 dies) around C3Q27 - and the latter being below our previous estimate of 768GB of HBM4E per GPU." "slightly trim estimates in the near-term due to a wider range of potential pricing outcomes for NAND through year-end and into C1H27." "For DRAM, we believe HBM supply/demand has actually tightened with pricing for both HBM4 and HBM4E even stronger than our prior expectations." "Overall HBM consumption for C2027 is actually increasing from 58.7B Gb to 61.5B Gb. We are also getting confirmation that memory suppliers are re-widening the HBM/DDR price premium..."