World's Largest Supernode: China-Made "Ascend 950" Interconnect Debuts at WAIC Computing power remains a major highlight at WAIC this year. Huawei’s Atlas 950 supernode hardware made its first public debut, drawing massive attention. As the world’s largest commercial supernode, it’s built specifically for trillion-parameter LLM training and inference. Its real significance goes beyond single-node performance—it marks a shift in domestic computing power from competing on individual GPUs to system-level mastery of supernodes and 10,000-card clusters. Data Source: The industry’s largest Ascend 950 supernode hardware debuts publicly for the first time, as of 2026.07.17 #WAIC2026# #Huawei# #Ascend950# #Supernode# #ComputingPower# #AIInfrastructure# Risk Disclaimer: Investment involves risk, including possible loss of principal. Any forecasts, projections, or opinions contained herein are for reference only and are not guaranteed to occur. The information in this material reflects prevailing market conditions and our judgment as of the release date, which are subject to change without further notice.

$MU $SKHY $DRAM China's compute is going vertical. Huawei just raised its top AI chip 20 to 50% in two months. Cambricon repriced 20 to 30% higher. Grey market HBM inside China runs several times what the rest of the world pays. “Sources say Huawei has raised the indicated price of its Ascend 950DT accelerator card to more than $36,900. Depending on contract terms, that represents a 20% to 50% increase from prices quoted to customers just two months ago.” “Huawei has publicly said the 950DT, its most advanced AI chip, will become available in 4Q26.”“Sources say Cambricon has repriced its next-generation chip, tentatively called the 690, at 20% to 30% above levels indicated two months ago.” (No list price given.) “Sources say HBM obtained through these [grey-market] channels typically costs several times more than what buyers outside China pay.” “Huawei has said its Ascend 950 series will use two proprietary HBM technologies: HiBL 1.0 for the 950PR and HiZQ 2.0 for the 950DT, though it has not disclosed where or how the memory is manufactured.” “The Ascend 950PR, which sold for around $8,900 per card at the start of 2026, now costs more than $11,800, an increase of about 30%. The older Ascend 910C board has also climbed from around $13,300 at the beginning of the year to more than $16,200.” “Iluvatar CoreX has doubled its GPU shipments to TikTok developer ByteDance this year to 100,000 units.” “DeepSeek reportedly plans to deploy at least 160,000 Ascend 950DT chips at a large data center under construction in Inner Mongolia, primarily for AI inference.”

🔌 GLM-5.3-Flash Served Its Viral Debut Entirely on Domestic Chinese Chips Zhipu's GLM-5.3-Flash — the 320B-A18B model revealed this week as the anonymous "Ox Alpha" — set usage records on OpenRouter and OpenCode during its undercover test. The company says all of that traffic was served by domestic Chinese chip clusters. Zhihu contributor 刘延 reconstructs how Zhipu lined up this infrastructure, and reads the official engineering details for hints about which chips are actually doing the work. The core judgment: the bigger story here is not the model itself, but that a frontier-level model handled global-scale, real-world inference on domestic silicon. 1️⃣ The timeline behind the launch The author pieces together a sequence from public reporting. 🔹 Zhipu was reported to have acquired an infrastructure company. 🔹 LatePost reported Zhipu had brought 50,000 domestic cards online; around the same time, its CodePlan subscription got cheaper with generous bonus quotas. 🔹 Ox Alpha went live anonymously and, in the author's words, blew up worldwide. 🔹 Zhipu then confirmed every request in that test ran on domestic chips. 🔹 The latest LatePost report puts the deployment at 100,000 domestic cards. Note the card counts come from media reports, not Zhipu itself. 2️⃣ The engineering: surviving 1M context on constrained hardware Zhipu's own statement is unusually specific about the constraints. The main bottleneck on these chips is memory capacity and bandwidth, and supporting a 1M-token context is the hardest part. The company's listed optimizations include trading compute for bandwidth and communication for memory, intra-node tensor parallelism for the linear attention and the LM head, ReplaySSM, W8A8 quantization, INT8/FP8/BF16 mixed cache quantization, and Layer Split. 3️⃣ Which chips? Reading the precision hints Here the author speculates, and it should be read as inference, not confirmation. 🔹 FP8 support suggests Moore Threads could be handling prefill, or possibly Hygon's DCU-3. 🔹 INT8 points toward Ascend 910B/C as the likely backbone. 🔹 No mention of FP4 suggests the newer Ascend 950 is probably not in the mix. 4️⃣ Why this matters If the reporting holds, this is the first time domestic Chinese chip clusters have carried a frontier model's global production traffic at this scale — including a free, record-breaking stress test from developers worldwide. The author treats it as a proof point: China's domestic chips are no longer just for training experiments or internal pilots, but can serve a top-tier model to the open internet. 🔗 Key links: Official announcement: Open weights (MIT): 🔗 Full Reading: #GLM# #Zhipu# #AIChips# #AIInfra# #Ascend# #Semiconductors# #OpenWeights#