Foveros 2.5D enables high-density interconnects and heterogeneous chiplet integration, giving designers flexibility to combine different dies, process nodes, and IP in a single package. Learn more: #IntelFoundry#

Chiplet architectures are reshaping semiconductor design. See how Intel Foundry's EMIB and Foveros advanced packaging technologies help enable high-performance, chiplet-based architectures. Learn more: #IntelFoundry# #AdvancedPackaging#

Engineering innovation can help drive sustainability. Intel Foundry technologies, including Intel 18A, Intel 14A—enabled by RibbonFET and PowerVia/PowerDirect—and advanced packaging technologies like Foveros and EMIB are designed to help customers achieve greater performance and deliver more compute with less power. #IntelFoundry# #Sustainability#

Heading into #DAC2026#? Visit us at booth #830# to learn more about Intel 14A, Intel 18A-P, EMIB-T, and Foveros technologies. From advanced process technologies to industry-leading packaging, Intel Foundry is helping customers bring the next generation of computing to life. #IntelFoundry#

AI needs the "brain power" of multiple chips. At Fab 9 in New Mexico, @Intel_Foundry creates systems of chips using Foveros 3D stacking to optimize space for laptops to be thinner with longer lasting batteries. 💻 Watch how Foveros is created 👇

APPLIED MATERIALS, INTEL TO CO-DEVELOP NEXT-GEN AI CHIP TECHNOLOGY $AMAT and $INTC are expanding their R&D partnership to develop next-generation transistors, interconnects and advanced packaging for AI chips. The work will span Applied’s new EPIC Center and Intel’s Oregon R&D campus, including development around Intel’s Foveros 3D stacking technology, with the goal of moving new AI-focused semiconductor technologies into high-volume manufacturing faster.

$INTC Advanced Packaging Plant in Malaysia Now Online, According to SemiAnalysis A growing share of South Korean HBM shipments is now heading to Malaysia, while shipments to Taiwan have fallen sharply Around $1.3 billion worth of HBM is now being exported to Malaysia, compared with less than $3 billion to Taiwan, down from more than $5 billion just a few months ago Since TSMC has no advanced packaging facility in Malaysia and other local players remain relatively small, SemiAnalysis argues that Intel is the most likely destination Intel recently completed the final phase of its $7 billion Project Pelican advanced packaging complex in Malaysia, which supports die preparation and advanced packaging flows including EMIB and Foveros

High quality call. The expert spent 31 years at $INTC, 24 of them inside the fabs, running 24/7 operations across lithography, dry etch and thin films metals as an area manager. He traces Intel's derailment to one call: for 10nm, Intel decided it did not need EUV, despite having been one of the largest investors in ASML to create the technology. The company committed to technical specifications that could not be delivered reliably without it, then tried to hit them with quad patterning. "Despite Intel being one of the biggest investors in ASML to create EUV technology a decade earlier, by the time that technology was ready, we said, 'Nah, we don't need it.' That was a watershed decision... Yields, costs, throughput, all of it suffered." The mechanism that turned a process error into a company-level failure is the IDM coupling. Intel products depend on Intel Foundry. When 10nm underdelivered, the product line had no competitive process to design onto, and the only remedy was outsourcing, which is why a meaningful share of Intel's chiplets are built at TSMC. Low internal volume then starved the fabs of the very thing they needed to recover. His framing of the node sequence is bracing: Intel 7, Intel 4, Intel 3 and 18A were a chain in which each node inherited the unresolved problems of the one before, and 18A arrived initially without yield or parametrics. He puts the effective slip on 18A at roughly two years. Process improvement is a data-limited exercise. TSMC runs full loading for Apple, AMD and NVIDIA, which generates enormous volumes of process data, which enables fast learning cycles, which sustains leadership, which attracts the volume. Intel is fabbing almost exclusively for Intel products, and Intel products have been weak for a decade. The data turns are not there. "They're basically only fabbing for Intel products, and Intel products have been struggling. The volume of data is just not there for Intel to innovate faster... I think sometimes the reason Intel hesitates, the reason they waffle a little bit on making claims is because of this, because they just can't get the data turns fast enough to know with confidence where they're at." He flags Foveros and wafer-level packaging as equally critical to 18A and increasingly the harder problem. Panther Lake does not ship without it, and a packaging failure destroys yield at a far higher cost per unit than a front-end failure, because you are scrapping fully processed die. Lip-Bu Tan's original position was that Intel would not commit to 14A without external customers putting skin in the game. The expert's point is that this position was internally incoherent with the stated commitment to remain an IDM. If Intel does not build 14A, Intel products cannot design competitive parts, so Intel products must be allowed to outsource wafers. Do that for a couple of years and the foundry loses its largest customer and is finished. He also thinks the original statement was a strategic error in communication terms, since no prospective customer is motivated by a vendor signaling it might stop investing. "Intel products cannot design competitive products if the foundry is stuck on an old node. If Lip-Bu stuck to that initial declaration, he is then required to allow Intel products to outsource their wafers. By default, over time, not very long either, within a couple of years, he puts his own foundry out of business, because his number one customer is Intel products." He knows that prospective customers have been running test chips, samples and data reviews with Intel Foundry for at least two years. The absence of commitment after that much engagement is itself the datapoint on process competitiveness. What could change it, in his view, is not purely technical. Two exogenous tailwinds are now in play. TSMC leading-edge capacity is on allocation, so second-source conversations are being driven partly by desperation rather than preference. And there is a political layer around domestic capacity that he assumes is present in the shadows of these decisions. He credits Lip-Bu Tan with identifying waste and making necessary decisions into a genuinely broken situation. His objection is to method rather than direction: capable long-tenured people pushed out because the incoming CEO did not know them, replaced by people brought in from adjacent industries. He also puts the start of the decline around 2012, well before Gelsinger, and characterizes Gelsinger's plan as broadly right but poorly executed and over-committed. Conclusion: Intel is obviously far behind TSMC when it comes to process know-how and yields, but has an opportunity in the coming years to pick up volumes as TSMC is at 100% utilization. Larger volumes should lead to better yields and increase the learning curve for Intel, but obviously, this remains a difficult story. TSMC is obviously far ahead and is building additional N3 and N2 capacity to address wafer supply shortages themselves. $INTC $TSM $ASML

I've been discussing Huawei's τ scaling (temporal scaling) with people recently, and noticed the conversation tends to stay at the surface level without reaching its substance — likely because many participants don't come from an EE background and aren't familiar with the classical meaning of τ in circuit theory. The very first time constant you learn in a circuits course is τ = RC: the resistance of a wire multiplied by its capacitance gives the order of magnitude of the time a signal needs to traverse that wire. The longer the wire, the greater the resistance and capacitance, and the slower the signal. Within this framework, the past sixty years of geometric scaling are reinterpreted as one particular implementation of temporal scaling. Transistors were shrunk to shorten switching delay; circuits were packed more tightly to shorten metal interconnects and reduce signal propagation delay. Geometric scaling was only ever the means — compressing delay was always the end. Huawei's thesis is that once geometric scaling stalls, you find other ways to keep compressing delay. As it happens, He Tingbo's τ scaling paper released its v2 a couple of days ago, expanding from 16 to 23 pages. I compared the two versions: the data and conclusions are unchanged. The additions are essentially responses to several points of criticism the industry raised about v1. Three are worth discussing. The most important addition is the test evidence now backing the previously bare claim of "41% energy efficiency improvement." In v1, that number had no baseline and no test conditions — the most obvious target for scrutiny. V2 supplies a full comparison table. The baseline is the 2025 Kirin 9030 Pro. Both chips use the same mature process node; the key difference is that the baseline uses a conventional planar design, while Kirin 2026 folds critical paths across two vertically bonded wafers. Folding shortens interconnects and reduces interconnect delay. The timing margin freed up on the critical path translates directly into a higher maximum clock frequency: 3.1 GHz at 1.1 V supply, 13% above the baseline. The "41% energy efficiency improvement" comes from a separate operating point specifically configured for an iso-performance comparison: voltage scaled down to 0.9 V, frequency scaled down to 2.5 GHz, with measured power at 25°C coming in at 0.59× the baseline. A back-of-the-envelope estimate checks out: dynamic power scales roughly with the square of supply voltage, so an 18% voltage reduction contributes about one-third of the power drop from the square term alone. Factor in the 9% frequency reduction and the interconnect capacitance eliminated by folding, and you land right around 0.59×. So the precise meaning of "41% energy efficiency improvement" is power reduction at iso-performance. In essence, the timing margin gained from folding is traded for lower power consumption; the efficiency gain comes from logic folding. As a side note, v2 also reports that power density after dual-layer stacking is actually 5.6% lower than the baseline. The second addition addresses the question peers are most likely to ask: 3D stacking has been around for years — AMD's 3D V-Cache and Intel's Foveros are both in volume production — so what's new about LogicFolding? To understand the paper's answer, you first need to know how two layers of silicon communicate. They rely on inter-layer bond pads, which function like elevators connecting the upper and lower floors. In prior production 3D stacking, bond pad pitch ranges from 9 μm to tens of micrometers, yielding roughly ten thousand connections per square millimeter — enough to attach a bus to an entire cache block. So the established design approach has been to move complete functional blocks wholesale onto the upper tier. AMD, for example, stacks an entire cache die on top of a processor die; the two tiers are designed independently and connected through an interface. But inside a chip, a single square millimeter contains hundreds of millions of transistors. If you want adjacent logic gates to sit on different tiers — one on top, one on the bottom — that connection density falls far short. Kirin 2026 brings bond pad pitch down to 1.5 μm, yielding 440,000 connections per square millimeter. That approaches the density of the top-level metal wiring inside a chip. Routing a signal across tiers costs roughly the same as routing it across metal layers within a single die. At this point, the two silicon layers merge into a single entity in the circuit sense. EDA tools can decide at the individual logic-gate level which gate goes on which tier, handing the problem to algorithms for global optimization — a completely different degree of design freedom from what came before. The paper also explains why they didn't take the more aggressive route of fabricating a second device layer directly on top of the first. That approach offers the finest inter-layer connectivity, but manufacturing the second layer requires high temperatures that damage the already-completed first layer. It isn't production-viable today. The third addition is thermal management. Vertical stacking significantly increases thermal density per unit area, and the lower die's heat dissipation path is blocked by the upper die. This is the first objection anyone raises about 3D stacking, and v1 did not address it in depth. V2 openly acknowledges that thermal management remains a key challenge for the LogicFolding architecture. The countermeasure is thermally-aware partitioning and floorplanning: during the design phase, high-power circuits are excluded from folding candidates, and the floorplan avoids placing high-power blocks in vertical adjacency to prevent hotspot superposition. Whether this strategy is a set of manually imposed engineering constraints or has already been codified into an automated flow within their internal EDA tools, the paper does not say. It only identifies a multi-physics tool chain as the single most important investment for the next decade. Combined with the measured data showing power density 5.6% below the baseline at the iso-performance operating point, the thermal concern has at least received a direct response. That said, this approach is fundamentally avoidance-based. As stacking grows to three or four tiers, the design space eligible for folding will be progressively squeezed by thermal constraints — a boundary the paper does not explore. Additionally, v2 includes a cross-sectional micrograph of the bond interface between the two wafers and explicitly states that wafer-on-wafer hybrid bonding is used. This spec is worth benchmarking against the industry: 1.5 μm pitch wafer-to-wafer hybrid bonding on a production logic chip has no precedent. TSMC's SoIC is currently in production at 6 μm pitch; Intel's Foveros Direct is at 9 μm. Impressive, to say the least. After comparing the two versions, I'm left with two questions. One is about equipment: who supplied the bonding tools capable of this spec? The paper says only that it is the result of years of process development across a multi-vendor ecosystem. The other is about EDA: designing two wafers as a single chip is beyond what any commercially available EDA tool can do today. The paper acknowledges this, stating only that methodological details will be "published within months." Yet the frequency table shows that the 2027-generation Kirin at 3.39 GHz is already tagged as having physical silicon, meaning this toolchain was up and running inside Huawei long ago — and has been validated on at least two product generations. My personal guess is that this EDA capability was built in-house by Huawei. If anyone has insight on this, I'd welcome the discussion.