#AdvancedPackaging#: TSMC says nobody else is in production at 5X reticle size — and C.C. Wei hints TSMC will step in if EMIB-T falls short From TSMC's 3Q26 #EarningsWatch# call (10/15), the CoWoS, Intel EMIB-T and GlobalFoundries exchanges in the speakers' own words: 🔹 Q (Charlie Chan, Morgan Stanley): "From what we're seeing, the reticle size is getting much bigger. … If some customer, they initially choose to use Intel's EMIB-T, and for some reason cannot get to sufficient demand, are you okay to bail out or support customers for the CoWoS version or capacity?" A (C.C. Wei, Chairman & CEO, TSMC): "So far, let me share with you today's situation. We are in the real-world production of 5X reticle size. I don't believe that anybody can do that today except TSMC, and the yield is excellent. So our customers are very satisfied with the result. And then we are working on the 9X reticle size and moving into the 14X reticle size. … But so far, CoWoS is still the number one choice for our customer. As time goes by, yes, our competitor offers a very competitive solution." 🔹 Backup plan? Jeff Su, TSMC IR: "If the competitor cannot deliver on their solution … will you be willing to be something like a backup plan?" C.C. Wei: "I try to avoid to answer it directly, but let me say that, yes, we will be. … Okay? And that gives you enough hint." 🔹 Q (Sahith Singh, Stifel Financial): "There was the announcement via GlobalFoundries that they would be providing silicon interposers to TSMC. And so I would love some color into how you're thinking through these strategic decisions in terms of procuring from some of the specialty foundries versus providing in-house." A (C.C. Wei): "We designed a deal with GlobalFoundries, and this is part of our overall strategy in the back-end supply. … Definitely, we have a little bit shortage on the back end, and we would like to work with our so-called partner with GlobalFoundries so that both TSMC and GlobalFoundries can support TSMC's customer for their product to be introduced with enough support on the capacity." 💡More: 🔗 $TSM $INTC $GFS

Larger packages, finer routing, and embedded functions are pushing advanced substrates toward application-specific designs. #semiconductor# #substrates# #advancedpackaging# #GlassSubstrates#

The difficulty in building a package digital twin goes beyond creating accurate electrical, thermal, or mechanical models. #semiconductor# #advancedpackaging# #digitaltwins# #chiplets# #semiocnductormanufacturing#

Rising power density and chiplet complexity drive thermal considerations earlier in the design process. #thermal# #datacenters# #multiphysics# #advancedpackaging# #3DIC# #semiconductor#

Chiplet architectures are reshaping semiconductor design. See how Intel Foundry's EMIB and Foveros advanced packaging technologies help enable high-performance, chiplet-based architectures. Learn more: #IntelFoundry# #AdvancedPackaging#

Intel Foundry developed a blueprint for hyper-large form factor chip packages and a void-free encapsulation process that helps improve reliability for next-generation AI and HPC. Learn more in our latest blog: #IntelFoundry# #AdvancedPackaging#

Advanced packaging is no longer just about adding CoWoS capacity. It is becoming a global manufacturing ecosystem. TSMC’s reported $2 billion, five-year manufacturing agreement with GlobalFoundries highlights an important shift in the AI semiconductor supply chain. Under the agreement, GlobalFoundries is expected to manufacture silicon interposers for TSMC at its Malta, New York facility, with production ramping up in 2028. The significance goes beyond geographic diversification. As AI accelerators integrate increasingly expensive GPUs, HBM stacks, and complex interconnect structures, qualified silicon interposer capacity is becoming just as important as packaging assembly capacity. This also creates an interesting opportunity for mature-node foundries. They do not necessarily need to compete with TSMC at the most advanced logic nodes to participate in the AI infrastructure boom. The next phase of advanced packaging competition may be less about who owns the entire process and more about who can build the most reliable, scalable, and geographically diversified supply chain. #TSMC# #GlobalFoundries# #CoWoS# #AdvancedPackaging# #AI# #Semiconductors#

🧠 Hot Chips 2026: AI's Memory Wall Is Becoming a Money and Packaging Wall Hot Chips 2026 is still producing the usual charts of larger chips and higher peak compute. But this year, memory vendors are becoming central to the AI hardware story. The reason is simple: adding more arithmetic is getting easier. Keeping those units fed is not. Zhihu contributor 乱序摸鱼 reviewed the conference's memory talks and traced a larger shift across Samsung, Micron, SK hynix, and emerging architectures such as HBF. His main takeaway: the boundary between compute and memory is starting to dissolve. 1️⃣ The Memory Wall has become a Money Wall AI is not merely consuming more memory. It is pushing the DRAM industry toward a far more silicon-intensive product. For the same capacity, HBM requires roughly 3× the DRAM die area of DDR. A wafer redirected to HBM can therefore deliver fewer total bits, even before packaging and yield are considered. At the same time, new DRAM capacity can take more than two years to become productive. AI accelerator demand changes much faster. The article cites a revealing mismatch: AI compute can grow around 3× every two years, while HBM bandwidth grows by less than 2× over the same period. HBM solves the bandwidth problem through massive parallelism: wider interfaces, more channels, more banks, TSVs, and advanced packaging. But the bandwidth is not free. Its cost appears elsewhere as silicon area, power, packaging complexity, and yield risk. 2️⃣ The HBM base die is turning into a SoC Traditional HBM had a clean division of labor. The upper DRAM dies stored data, while the base die handled interfaces, testing, and basic routing. HBM4 changes the economics. Once the base die moves to an advanced logic process, using it as an expensive wiring layer becomes increasingly difficult to justify. Samsung's roadmap therefore expands its role in stages. The shorter-distance PHY comes first. Then the memory controller moves down from the xPU, followed by telemetry, repair, testing, RAS, and potentially lightweight processing. This turns HBM from a passive device into something that understands its own banks, temperature, failure state, and access scheduling. But integration creates new tradeoffs. A shorter interface may reduce energy per bit while concentrating the same throughput into a smaller area, raising local power density and creating thermal hotspots. The base die is becoming smarter, but every new function brings more RTL, validation, thermal design, and software work. 3️⃣ Near-memory compute should be measured in bits avoided Putting compute near memory sounds attractive, but available silicon is not enough to justify doing it. The more useful question is: How much data movement disappears after this operator moves closer to memory? Filtering, compression, copying, search, and simple reductions can make sense near memory. They may scan a large dataset and return only a small result, eliminating enormous amounts of traffic. Dense matrix multiplication is different. Data moved into a GPU may be reused many times by Tensor Cores. Moving that computation into a constrained base die could create a weaker accelerator while adding a new compiler and runtime target. The author's rule is practical: move operations that significantly reduce data volume, not operations that merely fit into spare logic area. Samsung's zHBM takes this idea further by vertically stacking HBM above the xPU. The modeled design removes much of the millimeter-scale horizontal path between memory and compute. Samsung's public targets suggest around 70% lower I/O power and roughly 100 W saved in a modeled 1,200 W GPU system. Those are architectural targets rather than proven production results. The shorter electrical path also introduces harder problems in bonding yield, thermal design, power delivery, repair, and cross-die ownership. 4️⃣ HBF could add a cold tier, but software must make it work High Bandwidth Flash proposes another route: use stacked NAND to provide much more capacity at a lower cost than HBM. The tradeoff is severe. HBF may offer cheap capacity, but its bandwidth per gigabyte is roughly an order of magnitude lower. That makes it unsuitable as a drop-in replacement for HBM. Its strongest use cases are large datasets with consistently low access rates: 🔹 Cold MoE experts 🔹 Sparse KV cache 🔹 Prefix cache 🔹 Model state that must remain nearby but is not read every token Even MoE is not automatically a good fit. A single token activates few experts, but a larger batch combines expert requests from many users. The supposedly cold expert pool can become hot surprisingly quickly. The harder problem is system software. An HBM-HBF hierarchy needs placement, allocation, prefetching, request coalescing, cache policy, wear management, and runtime telemetry. The article's verdict is cautious: the architectural need is real, but HBF's path from an attractive model to a dependable product remains largely unproven. 5️⃣ HBM scaling is becoming a packaging problem SK hynix's presentation shows why adding more DRAM layers is no longer a simple capacity upgrade. Moving from 12Hi to 16Hi increases the number of layers by 33%, while the package height rises from roughly 720 μm to 775 μm, an increase of less than 8%. The remaining option is to compress everything. Dies become thinner, inter-die gaps narrower, and bump pitches denser. Warpage, underfill, thermal resistance, and bonding yield all become harder to control. Yield is also cumulative. A defect introduced early may only appear after many expensive processing and stacking steps have already been completed. For 20Hi and beyond, hybrid bonding becomes less of a futuristic option and more of a practical necessity. By removing conventional bumps and thick underfill gaps, hybrid bonding can reduce interconnect pitch and thermal resistance. It can also return part of the height budget to the DRAM itself. SK hynix estimates that, within the same overall stack height, core dies could be up to 24% thicker than with MR-MUF while using an interconnect pitch below 18 μm. That extra silicon thickness matters for mechanical strength, wafer handling, warpage, and manufacturability. 6️⃣ The real boundary being redesigned The most important Hot Chips 2026 memory story is not another increase in TB/s. It is the rising cost of the physical distance between data and compute. As arithmetic moves from FP16 to FP8 and FP4, chips can contain more MAC units than the system can consistently feed. Performance is increasingly lost to memory access, synchronization, interconnect power, thermal limits, and data placement. The optimization target is therefore expanding from one chip to the entire task path. HBM base dies are becoming logic devices. Memory controllers are moving closer to DRAM. Flash may become another managed AI memory tier. Compute and memory may eventually be vertically integrated. None of this eliminates complexity. It decides where that complexity should live so the whole system becomes more efficient. The author's final insight is a good one: Sometimes the best architecture does not make the road faster. It discovers that the trip never needed to happen. 🔗 Full analysis: #HotChips2026# #HBM# #AIInfrastructure# #Semiconductors# #MemorySystems# #AdvancedPackaging# #AIHardware#

Advanced Logic, HBM and Advanced Packaging (CoWoS and CoPos) depends on Applied Materials. TSMC depends on Applied Materials Samsung depends on Applied Materials SK Hynix depends on Applied Materials Intel depends on Applied Materials Terafab depends on Applied Materials See you on the call tomorrow. $AMAT

The advanced packaging race is heating up, but #TSMC# isn’t fazed by the growing buzz around #Intel’s# EMIB. CEO C.C. Wei says TSMC alone can mass-produce 5x reticle-size packaging at high yields—and it’s already pushing toward 9x.💡More: 🔗