Chiplet architectures are reshaping semiconductor design. See how Intel Foundry's EMIB and Foveros advanced packaging technologies help enable high-performance, chiplet-based architectures. Learn more: #IntelFoundry# #AdvancedPackaging#

Intel Foundry developed a blueprint for hyper-large form factor chip packages and a void-free encapsulation process that helps improve reliability for next-generation AI and HPC. Learn more in our latest blog: #IntelFoundry# #AdvancedPackaging#

🧠 Hot Chips 2026: AI's Memory Wall Is Becoming a Money and Packaging Wall Hot Chips 2026 is still producing the usual charts of larger chips and higher peak compute. But this year, memory vendors are becoming central to the AI hardware story. The reason is simple: adding more arithmetic is getting easier. Keeping those units fed is not. Zhihu contributor 乱序摸鱼 reviewed the conference's memory talks and traced a larger shift across Samsung, Micron, SK hynix, and emerging architectures such as HBF. His main takeaway: the boundary between compute and memory is starting to dissolve. 1️⃣ The Memory Wall has become a Money Wall AI is not merely consuming more memory. It is pushing the DRAM industry toward a far more silicon-intensive product. For the same capacity, HBM requires roughly 3× the DRAM die area of DDR. A wafer redirected to HBM can therefore deliver fewer total bits, even before packaging and yield are considered. At the same time, new DRAM capacity can take more than two years to become productive. AI accelerator demand changes much faster. The article cites a revealing mismatch: AI compute can grow around 3× every two years, while HBM bandwidth grows by less than 2× over the same period. HBM solves the bandwidth problem through massive parallelism: wider interfaces, more channels, more banks, TSVs, and advanced packaging. But the bandwidth is not free. Its cost appears elsewhere as silicon area, power, packaging complexity, and yield risk. 2️⃣ The HBM base die is turning into a SoC Traditional HBM had a clean division of labor. The upper DRAM dies stored data, while the base die handled interfaces, testing, and basic routing. HBM4 changes the economics. Once the base die moves to an advanced logic process, using it as an expensive wiring layer becomes increasingly difficult to justify. Samsung's roadmap therefore expands its role in stages. The shorter-distance PHY comes first. Then the memory controller moves down from the xPU, followed by telemetry, repair, testing, RAS, and potentially lightweight processing. This turns HBM from a passive device into something that understands its own banks, temperature, failure state, and access scheduling. But integration creates new tradeoffs. A shorter interface may reduce energy per bit while concentrating the same throughput into a smaller area, raising local power density and creating thermal hotspots. The base die is becoming smarter, but every new function brings more RTL, validation, thermal design, and software work. 3️⃣ Near-memory compute should be measured in bits avoided Putting compute near memory sounds attractive, but available silicon is not enough to justify doing it. The more useful question is: How much data movement disappears after this operator moves closer to memory? Filtering, compression, copying, search, and simple reductions can make sense near memory. They may scan a large dataset and return only a small result, eliminating enormous amounts of traffic. Dense matrix multiplication is different. Data moved into a GPU may be reused many times by Tensor Cores. Moving that computation into a constrained base die could create a weaker accelerator while adding a new compiler and runtime target. The author's rule is practical: move operations that significantly reduce data volume, not operations that merely fit into spare logic area. Samsung's zHBM takes this idea further by vertically stacking HBM above the xPU. The modeled design removes much of the millimeter-scale horizontal path between memory and compute. Samsung's public targets suggest around 70% lower I/O power and roughly 100 W saved in a modeled 1,200 W GPU system. Those are architectural targets rather than proven production results. The shorter electrical path also introduces harder problems in bonding yield, thermal design, power delivery, repair, and cross-die ownership. 4️⃣ HBF could add a cold tier, but software must make it work High Bandwidth Flash proposes another route: use stacked NAND to provide much more capacity at a lower cost than HBM. The tradeoff is severe. HBF may offer cheap capacity, but its bandwidth per gigabyte is roughly an order of magnitude lower. That makes it unsuitable as a drop-in replacement for HBM. Its strongest use cases are large datasets with consistently low access rates: 🔹 Cold MoE experts 🔹 Sparse KV cache 🔹 Prefix cache 🔹 Model state that must remain nearby but is not read every token Even MoE is not automatically a good fit. A single token activates few experts, but a larger batch combines expert requests from many users. The supposedly cold expert pool can become hot surprisingly quickly. The harder problem is system software. An HBM-HBF hierarchy needs placement, allocation, prefetching, request coalescing, cache policy, wear management, and runtime telemetry. The article's verdict is cautious: the architectural need is real, but HBF's path from an attractive model to a dependable product remains largely unproven. 5️⃣ HBM scaling is becoming a packaging problem SK hynix's presentation shows why adding more DRAM layers is no longer a simple capacity upgrade. Moving from 12Hi to 16Hi increases the number of layers by 33%, while the package height rises from roughly 720 μm to 775 μm, an increase of less than 8%. The remaining option is to compress everything. Dies become thinner, inter-die gaps narrower, and bump pitches denser. Warpage, underfill, thermal resistance, and bonding yield all become harder to control. Yield is also cumulative. A defect introduced early may only appear after many expensive processing and stacking steps have already been completed. For 20Hi and beyond, hybrid bonding becomes less of a futuristic option and more of a practical necessity. By removing conventional bumps and thick underfill gaps, hybrid bonding can reduce interconnect pitch and thermal resistance. It can also return part of the height budget to the DRAM itself. SK hynix estimates that, within the same overall stack height, core dies could be up to 24% thicker than with MR-MUF while using an interconnect pitch below 18 μm. That extra silicon thickness matters for mechanical strength, wafer handling, warpage, and manufacturability. 6️⃣ The real boundary being redesigned The most important Hot Chips 2026 memory story is not another increase in TB/s. It is the rising cost of the physical distance between data and compute. As arithmetic moves from FP16 to FP8 and FP4, chips can contain more MAC units than the system can consistently feed. Performance is increasingly lost to memory access, synchronization, interconnect power, thermal limits, and data placement. The optimization target is therefore expanding from one chip to the entire task path. HBM base dies are becoming logic devices. Memory controllers are moving closer to DRAM. Flash may become another managed AI memory tier. Compute and memory may eventually be vertically integrated. None of this eliminates complexity. It decides where that complexity should live so the whole system becomes more efficient. The author's final insight is a good one: Sometimes the best architecture does not make the road faster. It discovers that the trip never needed to happen. 🔗 Full analysis: #HotChips2026# #HBM# #AIInfrastructure# #Semiconductors# #MemorySystems# #AdvancedPackaging# #AIHardware#

Advanced Logic, HBM and Advanced Packaging (CoWoS and CoPos) depends on Applied Materials. TSMC depends on Applied Materials Samsung depends on Applied Materials SK Hynix depends on Applied Materials Intel depends on Applied Materials Terafab depends on Applied Materials See you on the call tomorrow. $AMAT

$INTC Advanced Packaging Plant in Malaysia Now Online, According to SemiAnalysis A growing share of South Korean HBM shipments is now heading to Malaysia, while shipments to Taiwan have fallen sharply Around $1.3 billion worth of HBM is now being exported to Malaysia, compared with less than $3 billion to Taiwan, down from more than $5 billion just a few months ago Since TSMC has no advanced packaging facility in Malaysia and other local players remain relatively small, SemiAnalysis argues that Intel is the most likely destination Intel recently completed the final phase of its $7 billion Project Pelican advanced packaging complex in Malaysia, which supports die preparation and advanced packaging flows including EMIB and Foveros

AEMC (Advanced Echem), a specialty chemical maker and key TSMC supplier, will invest NT$4.52 billion (US$140M) on a new chemical plant and R&D lab in the Longtan Science Park in north Taiwan due to strong demand, media report. AEMC’s top products are used in 2nm production and advanced packaging (Photoresist, EBR, BARC, 2D/3D wafer-level packaging materials, more). $TSM #semiconductors#

$TSM Vice President of Advanced Packaging: "Foundries can scale up the optical engine, but the real bottlenecks to large scale deployment lie elsewhere... Including lasers, optical fiber, fiber-optic connectors, and test" (UDN) Just some bucket ideas: Lasers: $LITE, $SIVE, $COHR, LandMark (3081), LuxNet, Sumitomo, Furukawa Optical fiber / FAU: Foci, Browave, $GLW, Sumitomo Fiber Optic / CPO Connectors: BizLink, $GLW , Fujikura, Nextronics, COXOC CPO testing: MPI (6223), Advantest, $FORM, Msscorps, $KEYS, Chroma (disclosure: exposure to theme above, individual names not named by TSMC) There are others I like as well, such as ShunSin, which now has explicit TSMC COUPE exposure but probably belongs under a different category like packaging/integration. eg. "Foxconn unit ShunSin confirms TSMC COUPE partnership" I don't think there's anything too new vs. H1, aside from ongoing news (eg. FAU looks like there will have a demand imbalance in 2027, from a report last week). But it's helpful to reiterate overall beneficiaries from time to time...

Panel-level advanced packaging is exploding According to Yole’s 2026 report, the advanced packaging market is expected to post a 9.1% CAGR from 2025 to 2031 PLP is growing much faster Yole expects PLP revenue to rise from $312 million in 2025 to $2.959 billion in 2031, representing a 45.5% CAGR over the same period

Rumor: Intel Malaysia took over some advanced packaging for TSMC due to a surge in orders for CoWoS packaging by a major mutual client, media report, adding ASE, Unimicron, Gudeng Precision and others are also expected to benefit from the move. TSMC is expected to ship more advanced chips as the packaging bottleneck eases. $INTC $TSM $ASX $GOOGL $NVDA #semiconductors#