Tomorrow is Tokyo Game Show!! The next day I am getting up early to stream Silent Hill f! Straight after my stream I need to travel a few hours away to check into my hotel for Oarai Firework Festival (CosFes) the next day. The next day will be the cosplay event! Then I need to travel back to Tokyo after the event, late in the eveing. Then the next day I need to get up early again to go and shoot a sponsored cosplay. It's already late, so i have to edit and prepare the photos and videos as soon as I get home. The next day is a video shooting in Shibuya, requiring two cosplays, and again very fast turn-around for the results. And the last day of the month will be The Primals concert! I am a little stressed, but I'm going to get this all done!! FIGHT-O!!🦾

For decades, every new node had to cut cost per transistor. In the AI era, the measure is "value per transistor," based on performance, power efficiency, thermals, and packaging, optimized for the full system, according to @Intel_Foundry’s VP and GM of Manufacturing Development, Chris Auth. @intel $INTC

An AI factory's long-term efficiency starts with decisions made before deployment. At the Six Five Summit, @Lenovodc's Wil Wellington explains to @nickpatience how they evaluate site readiness, power, thermals, and rack density up front, and use Neptune warm-water liquid cooling to keep the environment tuned long after go-live. $LNVGY

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Samsung's custom HBM talk is great. Building a base die on leading edge node affords the following advantages: 1) The TSV PHY block gets smaller enabling more parallel TSVs 2) The D2D PHY gets smaller which means that silicon area on both the base die and the XPU gets smaller. This opens up space on XPU and base die for other functions. 3) The memory controller usually on the XPU die, can be integrated on the base die. 4) Advanced RAS functions will be integrated into the base die. Thermal, voltage, process, and aging sensors enable real-time, high-speed telemetry. The SRAM on advanced base die can be used to perform repair and correction. 5) The custom die will incorporate more proessing elements bringing some level of compute to the base die. 6) The extra space can also be used for memory extension controller so that expansions to things like HBF are possible. 7) Eventually, the plan is to stack the custom base die + hbm stack (more like 4 high due to thermals) on top of compute --> zHBM. The main thermal problem comes from D2D block, but vertical stacking means that the D2D will be more distributed (edge vs area) thereby helping thermals. 8) Samsung prefers the use of proprietary D2D, rather than UCIe because they feel UCIe is larger, and not quite energy efficienct.

What's the next step change in chip packaging technology? @bubbleboi: "The main difference between EMIB and CoWoS is CoWoS relies on what we call silicon interposers. They're like these huge plates where you put the chips on, and you start etching channels in between through the interposers." "An effect of that is that heat dumps into the interposers, just like anyone knows when they heat up popcorn, things expand and contract, and this creates worse yield." "NVIDIA's already seen this. Part of the reason why Blackwell had trouble ramping was all thermals, the package warping. That's a huge issue." "I think even TSMC knows it's a huge issue because in their further along roadmap, they don't really plan on adopting that for much longer. They're now going to a more Intel style thing where you use little bridges... smaller pieces of silicon to connect just the relevant parts." "What that effectively does is cut your costs 'cause you're using way less silicon, the thermals, the communication, it's centralized in one area."