TSMC’s US$100 billion addition to its US investment plans – now totaling $265 billion – will expand TSMC Arizona to 12 fabs, but the market fears the move will hurt profitability, media report, noting construction costs are 4 to 5 times higher than Taiwan (from TSMC’s CFO). The fear is TSMC’s gross margin may fall below 65%, given margin pressure from ramping 2nm (3-4 percentage points) and overseas fab investments (2-3 percentage points). The report argues such worries are overdone. TSMC is playing the long game, building critical AI infrastructure for the long haul – with capex raised to $60-$64B from $52-$56B previously, and it takes 5-years years for advanced fabs to ramp up to mass production, from the initial groundbreaking. Operationally, mass production at TSMC Arizona means costs go down as fabs ramp up through volume and efficiency gains. Production lines improve as workers better understand their jobs; construction improves the same way. $TSM #semiconductors#

TSMC’s Q2 net income jumped 77.4% YoY, yet $TSM closed 2.3% lower. 📉 AI optimism had already raised expectations. Now margins are the next test. See what could shape TSMC’s next quarter 👇 #WallStreetMonth#

TSMC’s Arizona fab posted a Q1 profit of NT$18.8 billion, already surpassing last year’s full-year profit of NT$16.1 billion. Meanwhile, JASM’s Kumamoto fab recorded a NT$900 million profit, marking its first profitable quarter since mass production began at the end of 2024. With advanced process nodes and CoWoS advanced packaging capacity now in severe shortage, TSMC will need to accelerate capacity expansion even more aggressively — even without major price increases — in order to meet customer demand. Under a relatively conservative expansion scenario, overflow orders are already beginning to shift toward Intel and Samsung. $INTC $TSM

👀 #TSMC#'s COUPE on Substrate tech is expected to hit mass production in 2H26 — and if #CPO# gains traction in AI servers, #NVIDIA# may look to lock in high-end substrate capacity early via long-term deals. 💡More: 🔗

🔥 #TSMC# sees the global chip market topping US$1.5T by 2030 and is positioning for a major share, with its #2nm# and A16 chips projected to grow at a 70% CAGR through 2028. 💡More: 🔗

TSMC Expands Outsourcing of Key Packaging Step CoW… Expected to Ease AI Chip Manufacturing Bottleneck TSMC is expanding outsourced production of a major process step for artificial intelligence (AI) chips. The move is seen as a step toward resolving the bottleneck in AI chip manufacturing. Much of the volume TSMC had been handling in-house is set to go to outsourced semiconductor assembly and test (OSAT) firms, and a large-scale wave of equipment investment is expected to follow. According to industry sources on the 4th, TSMC has decided to place additional CoW (chip-on-wafer) packaging volume — part of the CoWoS process used to manufacture AI chips — with ASE and other OSAT providers. In response, major OSAT companies are moving ahead with equipment orders to build new production lines. Purchase order (PO) discussions are also reportedly underway with Korean materials, components, and equipment suppliers. The specific investment scale has not been disclosed, but capacity is expected to be expanded substantially versus current levels. CoWoS is TSMC's 2.5D packaging technology, used in building AI chips. A processor (SoC) for AI workloads, such as a GPU, sits at the center with high-bandwidth memory (HBM) placed around it, and an intermediate substrate called an interposer is used to connect the two. TSMC refers to the step of attaching the chips to the interposer as CoW, and the step of bonding that interposer to the main substrate as WoS (wafer-on-substrate). Until now, TSMC has mainly outsourced WoS, the bonding to the main substrate. ASE, Amkor, and SPIL have been producing it under technology licenses from TSMC. Some CoW work was also outsourced, but only in limited volumes. The decision to significantly expand CoW outsourcing this time is attributed to the persistent bottleneck in AI chip manufacturing. Demand has surged as not only global AI chip designers (fabless firms) led by Nvidia, but also AI data center operators, move to develop and deploy their own custom silicon. TSMC is estimated to hold roughly 90% of the global AI chip manufacturing market. With demand continuing to grow and TSMC's own capacity insufficient to meet it, the company is looking to increase outsourcing. "TSMC has continued to invest in packaging capacity for AI chip manufacturing, but it is still being criticized for bottlenecks at the packaging stage," an industry official said. "This expansion of outsourcing is an attempt to scale up capacity together with its key OSAT partners, as market demand keeps expanding." As OSATs receiving CoW volume from TSMC ramp up equipment investment, back-end materials, components, and equipment suppliers are also expected to benefit. Investment is seen concentrating in particular on dicing — cutting wafers and interposers — and on the bonding processes that join wafers to interposers. According to multiple sources in the Korean equipment industry, discussions on supplying CoW-related tools are underway in the laser processing and bonding segments. $ASX $AMKR

$TSM $MU $SKHY $DRAM TSMC's SoW-X: 64 HBM stacks on a single wafer. Today's best? 12. Today (CoWoS): 8 to 12 HBM stacks 2028 (CoWoS): 20 HBM stacks 2029 (CoWoS): 24 HBM stacks 2029 (SoW-X): 64 HBM stacks The leap is staggering.

Key takeaways on TSMC's next-generation advanced packaging, CoPoS (publicly available technical details omitted): 1. CoPoS is currently expected to enter mass production in 2H28. It is designed to improve the economics of ultra-large packages above the 9.5x reticle-size class, with NVIDIA’s Feynman AI chip a potential first adopter. 2. According to industry checks, glass is used in two distinct places (dimensions in mm): → 310 x 310 temporary glass carriers → 250 x 250 (pilot) / 510 x 515 (mass production) glass panels, processed and later cut into individual glass core substrates 3. The glass core substrate is essentially a three-layer structure: a glass core sandwiched between ABF (ABF-GCP) build-up layers on both sides. The widely discussed glass processing challenges, such as TGV formation and copper filling / metallization, are tied to this part of the stack. 4. Common misconceptions about CoPoS: → ❌ Misconception 1: CoPoS uses a glass interposer. ⭕️ Correction: The glass is not an interposer. The interconnect role is instead handled by the chip-side RDL, plus the TGV/Cu interconnects and ABF build-up layers in the glass-core substrate stack. → ❌ Misconception 2: Glass replaces ABF. ⭕️ Correction: As the substrate architecture above shows, glass and ABF coexist. → ❌ Misconception 3: Chips sit directly on glass. ⭕️ Correction: Chips are attached to the ABF build-up surface of the glass core substrate. 5. CoPoS should extend and reinforce TSMC’s leadership in advanced packaging, potentially giving that advantage visibility through around 2032.