AI rack power density is entering a new era. OCP’s M+ Diablo architecture introduces a ±400V DC sidecar to support rapidly rising AI power requirements. With Google, Meta, and Microsoft contributing, data-center power architecture is shifting from a supporting function to a critical bottleneck—and competitive advantage—for AI infrastructure.

$AVGO Taiwan’s ODM ecosystem is becoming a critical backbone of open AI networking. Broadcom highlights local partners supporting Tomahawk 5/6 and Jericho 4 platforms, including Alpha Networks, Accton, Delta, QCT, UfiSpace, Wistron, and WNC. Taiwan’s role is expanding from manufacturing into core AI infrastructure integration.

GlobalFoundries and Corning jointly demonstrated an optical interconnect solution that combines a silicon photonics (SiPh) chip with a detachable GLASSBRIDGE™ connector. For the first time, they achieved a fully detachable GLASSBRIDGE™ connector capable of handling up to 280 mW of optical power. The optical interface integrates GF’s silicon photonics platform, featuring SiN spot-size converters (SSCs) and a V-groove edge-coupling structure, with Corning’s GLASSBRIDGE™ connector technology, which utilizes low-loss ion-exchanged glass waveguides. The GF PIC expands the optical mode to match the 9 µm mode field diameter of the glass waveguide, while Corning’s waveguide routes the light to a connector interface compatible with standard MT ferrule connectors.

At IEEE ECTC 2025, #NVIDIA# proposed replacing polarization-maintaining fiber (PMF) with single-mode fiber (SMF) by integrating an active polarization tracking circuit directly into the silicon photonics (SiPh PIC) chip. The system dynamically stabilizes the optical signal’s state of polarization in real time. Although insertion loss and power consumption increase, the approach significantly reduces cost and improves supply chain flexibility, making it more suitable for large-scale AI data center deployments.

Over the past three decades, the global semiconductor industry was built on a highly efficient model of specialization. The United States controlled chip design, EDA, IP, and end-platform ecosystems. Taiwan became the center of advanced foundry manufacturing and packaging. South Korea dominated DRAM, NAND, and memory supply. Japan retained key positions in materials and equipment. China provided massive electronics manufacturing capacity and end-market demand.

Driven by the success of NVIDIA’s system-level architecture, HBM (High Bandwidth Memory) has effectively become the default memory configuration for high-end AI accelerators. In today’s AI infrastructure, memory is no longer a secondary component — it is a performance-defining element. You can think of HBM as the most premium real estate in a megacity. The location is unbeatable: it sits extremely close to the compute die, connected through an interposer with thousands of ultra-wide data paths. The infrastructure is top-tier: 3D die stacking, TSV vertical interconnects, and advanced packaging technologies such as CoWoS enable unprecedented bandwidth density.

Eric Schmidt was invited to speak at the commencement ceremony at University of Arizona, but was met with heckling and boos from tens of thousands of students in attendance. During his speech, he acknowledged graduates’ concerns about AI-driven job displacement and the uncertainty surrounding the future. He emphasized that humans must shape AI through values, responsibility, and agency, while also expressing optimism about AI’s potential in science, healthcare, and other fields. But the students clearly were not buying it.

TSMC’s Arizona fab posted a Q1 profit of NT$18.8 billion, already surpassing last year’s full-year profit of NT$16.1 billion. Meanwhile, JASM’s Kumamoto fab recorded a NT$900 million profit, marking its first profitable quarter since mass production began at the end of 2024. With advanced process nodes and CoWoS advanced packaging capacity now in severe shortage, TSMC will need to accelerate capacity expansion even more aggressively — even without major price increases — in order to meet customer demand. Under a relatively conservative expansion scenario, overflow orders are already beginning to shift toward Intel and Samsung. $INTC $TSM

According to a report by Bloomberg, Dutch semiconductor equipment giant #ASML# has announced a partnership with India’s Tata Group to jointly advance India’s 12-inch wafer fab project, with the goal of establishing domestic chip manufacturing capabilities in India. For India, this is not merely a single investment project, but is widely viewed as an important step toward challenging the semiconductor supply chain dominance of Taiwan, South Korea, and China. According to information released by both parties, ASML will provide technical support for Tata Group’s 300mm (12-inch) wafer fab located in Gujarat. The facility is expected to manufacture semiconductor products for applications including automotive, smartphones, and AI.