SemiVision 🇹🇼 👁️👁️
@semivision_tw
Expertise in Semiconductor Industry │Silicon Photonics│AI Industry│Supply Chain│ASIC│Ecosystem │Food │Travel
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AI clusters have expanded from thousands of GPUs to tens of thousands, and increasingly toward hundreds of thousands of accelerators. Once a training or inference workload spans such a massive number of processors, network latency, bandwidth, radix, topology, power consumption, and reliability directly determine accelerator utilization.
If GPUs spend time waiting for data from other GPUs, memory pools, or remote compute resources, theoretical FLOPS become far less meaningful.
This means that, in the AI era, network utilization increasingly determines compute utilization, while connectivity efficiency increasingly determines the efficiency of intelligence production.
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Latitude divides the optical-interconnect design space into five scales: waveguides with roughly 0.5 µm core cross-sections; device libraries with footprints of around 10–500 µm; optical engines in the 10–25 mm range; packages in the 50–80 mm range; and finally the rack, at roughly two meters. Its central idea is straightforward: from waveguide to rack, each physical scale sets constraints for the next one; from rack back to waveguide, measured device behavior must continuously be used to recalibrate the models.
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This architectural transformation is occurring alongside an extraordinary expansion in infrastructure scale.
At FIT Tech Day, Lumentum highlighted how the largest single-site AI infrastructures are increasingly being discussed in terms of gigawatts rather than megawatts. The presentation used 1 GW of IT power as an important reference point, corresponding roughly to the power scale of approximately 1.1 million H100-equivalent accelerators.
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At the #ECOC# Exhibition, Lumentum, Qualcomm, and Corning Incorporated are demonstrating a high-density optical die-to-die architecture using 1060 nm VCSELs to support high-bandwidth, low-power, and low-latency links over multimode fiber.
The demonstration combines Lumentum's VCSEL platform, Qualcomm's D2D interface technology, and Corning's fiber connectivity - showing a practical path toward compact, energy-efficient optical links for next-generation Al systems.
Source: $LITE
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TSMC’s A14 roadmap is starting to take shape.
According to Taiwan’s Commercial Times, #TSMC# is preparing a multi-generation production cluster for N3, N2, A16, and A14, with Hsinchu’s Fab 20 and Taichung’s Fab 25 playing key roles.
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The four plenary keynotes at #ECOC# 2026 collectively presented a remarkably coherent technology roadmap.
Peter Winzer of Ciena approached the problem from the perspective of AI cluster architecture, examining how the continued expansion of GPU and XPU clusters is forcing optical connectivity closer to compute through scale-up, scale-out, and scale-across architectures.
Patrick Vandenameele, CEO of imec, addressed the same challenge from a semiconductor technology perspective, arguing that future AI scaling can no longer rely on CMOS alone. Silicon photonics, 3D integration, advanced packaging, and electronics will increasingly need to evolve as part of a unified technology platform.
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China’s CCTV has released a hypothetical map of missile targets in Taiwan.
Apparently, Hsinchu Science Park looks pretty safe. 😅
The fabs can keep running.
new from 2025/12
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If there is one sentence that captures the industry direction revealed by the first group of papers at #ECOC# 2026, it is this: the most important change is no longer simply pushing optical communications from 800G to 1.6T, and then from 1.6T to 3.2T.
Instead, the industry is beginning to confront a much broader question: as each lane becomes faster, optical engines move closer to compute silicon, and the number of fibers continues to increase, how can the entire system still be manufactured at scale while keeping power consumption, yield, packaging complexity, testing requirements, and cost under control?
This is what makes ECOC 2026 particularly important.
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#Tower# Semiconductor and #NewPhotonics# have begun high-volume shipments of laser-integrated, serviceable optical-engine PICs supporting 800G to 1.6T, with CPX MSA-compliant 6.4T NPO chipsets planned for volume production in 2027.
Built on Tower's market-leading PH18DA silicon photonics platform, these scale-ready solutions integrate InP lasers with high-performance photonic circuits across FRO, LRO, LPO, XPO and NPO architectures- delivering greater bandwidth density, power efficiency and reliability.
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#Marvell# As Al inference scales, memory access has become as critical a constraint as compute performance. Marvell is demonstrating Photonic Fabric technology at Booth 704 at Al Infra Summit 2026, showing how optical connectivity creates a shared memory tier across multiple racks.
The platform enables low-latency memory sharing across up to 16 hosts spanning multiple racks at distances up to 30 meters, offloading warm KV cache blocks to support large context length, high concurrency, and long-horizon agentic inferencing. Integration options include both server-level and XPU package-level deployment.
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Samsung Electro-Mechanics × Qualcomm: Organic Bridge for AI Packaging
Samsung Electro-Mechanics and Qualcomm are reportedly developing Organic Bridge technology for high-density interconnects between logic and HBM in AI/HPC packages.
Unlike Intel’s EMIB, which uses an embedded silicon bridge, the approach integrates fine-pitch interconnects directly into the organic substrate, targeting lower cost and simpler processing.
2.5D → 2.1D
L/S: 9/12 μm → 2/2 μm
The key trend: organic substrates are moving closer to interposer-level interconnect density.
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"In this area—how to maintain Taiwan’s energy security—I think Taiwan has actually made greater strides than many people realize... We see Taiwan developing a range of options and tools to extend its energy resilience in those more extreme circumstances...
So, I think the question isn't so much, from international observers' perspective, "how long will Taiwan’s energy resources last?" I think the more pertinent question is how long can the global economy continue to operate at full strength if they don't have access to commerce and trade from Taiwan."
—— AIT Director Raymond Greene, Whole of Society Defense Resilience Forum, September 19, 2026
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#Samsung’s# HBM4 Yield Reportedly Reaches 80%: Competition Is Shifting From “Technology Catch-Up” to Volume Expansion
South Korea’s Seoul Economic Daily reported on September 20, citing industry sources, that Samsung Electronics’ HBM4 yield has improved from below 60% during the initial mass-production stage to approximately 80%.
Samsung is now reportedly planning to increase its overall HBM monthly wafer input from around 180,000 wafers in 2026 to approximately 250,000 wafers in 2027, representing an increase of nearly 40%.
The key shift is clear: the HBM4 race is moving beyond technology qualification and yield improvement toward large-scale capacity expansion and customer allocation.
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Big thanks to #財報狗# ( @statementdog ) for inviting me to join their podcast! 🎙️
We had a great conversation about the semiconductor industry, technology trends, and what’s happening behind the scenes.
If you understand Chinese, give it a listen! 😄
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Please make more 😝
#TSMC# Is Becoming Taiwan’s Unexpected Baby-Boom Hero 👶
Taiwan’s birth rate keeps falling—but “TSMC babies” are proving surprisingly resilient.
In 2025, Taiwan recorded just 107,812 births, down 20.05% YoY from 134,856. Meanwhile, babies born to TSMC families declined only 4.9%, from 2,450 to 2,331.
That means roughly 1 in every 46 babies born in Taiwan comes from a TSMC family—about 2.2% of all newborns.
The contrast is even more striking over time. From 2020–2025, employees of TSMC and VisEra welcomed 14,767 babies, averaging around 2,461 per year.
TSMC employees aged 20–64 represent only about 0.54% of Taiwan’s population in the same age group, yet their babies account for roughly 2.2% of national births—a roughly 4× difference.
Of course, semiconductor technology isn’t the secret ingredient.
Compensation and job stability matter, but so does corporate support: TSMC offers 12 weeks of maternity leave for the first child, 16 weeks for the second, and 20 weeks for the third and beyond, alongside fertility-treatment leave, egg-freezing leave, childcare leave, and work-from-home days.
TSMC also operates four preschools across Hsinchu, Taichung, and Tainan, serving up to 528 children aged 2–6, with childcare available for extended hours.
Perhaps Taiwan has discovered another strategic role for TSMC:
Advanced chips, advanced packaging… and advanced family planning.
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#TSMC# Is Becoming Taiwan’s Unexpected Baby-Boom Hero 👶
Taiwan’s birth rate keeps falling—but “TSMC babies” are proving surprisingly resilient.
In 2025, Taiwan recorded just 107,812 births, down 20.05% YoY from 134,856. Meanwhile, babies born to TSMC families declined only 4.9%, from 2,450 to 2,331.
That means roughly 1 in every 46 babies born in Taiwan comes from a TSMC family—about 2.2% of all newborns.
The contrast is even more striking over time. From 2020–2025, employees of TSMC and VisEra welcomed 14,767 babies, averaging around 2,461 per year.
TSMC employees aged 20–64 represent only about 0.54% of Taiwan’s population in the same age group, yet their babies account for roughly 2.2% of national births—a roughly 4× difference.
Of course, semiconductor technology isn’t the secret ingredient.
Compensation and job stability matter, but so does corporate support: TSMC offers 12 weeks of maternity leave for the first child, 16 weeks for the second, and 20 weeks for the third and beyond, alongside fertility-treatment leave, egg-freezing leave, childcare leave, and work-from-home days.
TSMC also operates four preschools across Hsinchu, Taichung, and Tainan, serving up to 528 children aged 2–6, with childcare available for extended hours.
Perhaps Taiwan has discovered another strategic role for TSMC:
Advanced chips, advanced packaging… and advanced family planning.
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#SKhynix# Completes #HBM4# Internal Qualification: HBM Is Entering the Era of “Custom Base Die” Competition
SK hynix says it has completed internal qualification for its next-generation HBM4 and established a mass-production system ready to support customer shipments.
HBM4 is not simply an upgrade in bandwidth and stack height. One of the more important architectural changes is the introduction of customer-specific logic/base dies, enabling much deeper co-design between HBM and AI accelerators.
This marks an important shift in the HBM market: competition is expanding beyond memory performance and manufacturing yield toward custom logic, system optimization, and tighter integration with AI accelerator architectures.
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Apply plz
NVIDIA interns. This is an incredible time to be in technology. Loved having you for the summer.
Come back and do your life’s work at @NVIDIA.
Over the past two years, the AI server value chain has revolved around GPUs and HBM. Investors focused on HBM3E and HBM4 supply, pricing, yields, customer qualifications, and capacity allocation. Capital expenditure followed the same direction, flowing into advanced DRAM, CoWoS and other 2.5D packaging capacity, ABF substrates, testing equipment, cooling systems, and AI server infrastructure.
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