Token is the unit. Attention is the operation. The KV cache is the memory that lets attention reuse the past. Here is the map that connects all three. An LLM writes one token per pass through the model, from top to bottom. Pass 1 is prefill. The whole prompt goes in at once. At every layer, each position produces q, k, and v. Attention matches queries to keys and blends values. An MLP follows, and a new hidden state moves to the next layer. Each layer saves its K and V in the cache. At the bottom, the hidden state at the final position becomes scores over the vocabulary. Under greedy decoding, the highest-scoring one becomes the first new token. That token feeds back, and decode begins. Every pass after the first carries only the new position. At each layer: read the weights, compute the new q, k, and v, read the past K and V, run attention over the cached history plus the new pair, run the MLP, and append the new k and v to the cache. Earlier tokens never move through the layers again. Their cached K and V preserve what attention needs to reuse from them. That is what turns inference into a hardware problem. During prefill, one weight read from HBM can serve many positions in the prompt. During decode, the same read may serve only one new position. Add a growing cache that must be revisited on every pass, and generating a single token can require an enormous amount of data movement. Capacity, bandwidth, and locality often set the limit, not arithmetic alone. A long context window is therefore a memory budget before it is a product feature. Serving systems are also beginning to place prefill and decode on different hardware, because the two phases put very different demands on the machine. Keep the map. Much of modern AI infrastructure hangs from it. Quantization changes how weights and caches are stored and moved. GQA shrinks the cache. FlashAttention changes data movement. MoE changes which weights are read. Speculative decoding changes the loop itself. The same map extends to batching, latency, throughput, context length, memory hierarchies, interconnects, serving architecture, and the chips built to run it all. Different techniques. Different tradeoffs. The same machine underneath.