Evidence-first AI semiconductor analysis: what new silicon claims prove, where bottlenecks move, and whether gains survive at system and economic scale.
OpenAI’s “AI builds AI” loop is becoming more explicit.
Two recent roles focus on using RL, tool use, and evaluation across RTL generation, verification, and physical design, plus the software infrastructure connecting those experiments to EDA tools.
This follows OpenAI’s claim that its models helped move Jalapeño from initial design to tapeout in nine months.
The signal is not just one fast chip project. OpenAI is building a repeatable AI-assisted chip-design workflow.
My take on why trustworthy feedback becomes the next bottleneck:
Research Engineer, AI for Chip Design
Software Engineer, AI for Chip Design