tphuang(@tphuang):CXMT announces G5 platform as a 12nm product. Storage-capacitor aspect ratio 45:1, DRAM-adapted HKMG, core functional-area height down to 6,762nm, plus a full-lifecycle digital-twin R&D line that reportedly cut new-process development time by ~40%. This is smaller than Micron's D1b platform, which was the previously known tightest non-EUV DRAM process. Says to increase # of die by > 50% vs G4 -> Die size shrunk by close to 40% for same memory. This is essentially a 2 to 3 node jump from D1z to D1b/c.

2026.09.20 11:16

CXMT announces G5 platform as a 12nm product. Storage-capacitor aspect ratio 45:1, DRAM-adapted HKMG, core functional-area height down to 6,762nm, plus a full-lifecycle digital-twin R&D line that reportedly cut new-process development time by ~40%. This is smaller than Micron's D1b platform, which was the previously known tightest non-EUV DRAM process. Says to increase # of die by > 50% vs G4 -> Die size shrunk by close to 40% for same memory. This is essentially a 2 to 3 node jump from D1z to D1b/c.