🚨 JAPANESE STOCKS ARE RALLYING ACROSS THE BOARD TODAY Toyota: +2.15% Kioxia: +2.59% Mitsubishi Heavy: +2.09% Advantest: +1.53% Mitsubishi UFJ: +1.27% The Nikkei still finished slightly in the red due to weakness in a handful of heavyweight stocks. Under the surface, Japan was VERY green today.

Just some consolidated updates on memory: - $MU leads new 1.5T Yen investment in Hiroshima ~$9.3B. (bullish read through for Disco, Advantest, Resonac, Towa) since capex is localized. - Morgan Stanley pointed out NAND will continue to be in short supply into 2027 so $SNDK / Kioxia type players are happy alongisde $SIMO and upstream. - MS remains especially positive on Macronix/Winbond - UBS expects the average price of DDR contracts in the Q3 2026 to increase 32% | 18% Q4, vs. 17% and 12% est. - UBS expects NAND flash to be raised 30% from prev quarter. - Samsung reportedly plans 20% DRAM hike Q3. TrendForce recently forecast DRAM contract prices to rise 13 to 18 percent in the third quarter from the previous quarter, so this hike beats expectations. Something to note: Lot people see 20%... and don't think it's a lot compared to the 70-80% from previous quarters. But if you hike something by 100%, then hike something by 100%, then hike something by 30%, it's a lot more than people estimate since it's compounded. Similar to tracking inflation. I've already made projections going into 2028 from the start of the year on my memory names... I'm just sitting back and watching things play out through all the "memory optimization" and "they can't keep price hiking like this!" noise.

$TSM Vice President of Advanced Packaging: "Foundries can scale up the optical engine, but the real bottlenecks to large scale deployment lie elsewhere... Including lasers, optical fiber, fiber-optic connectors, and test" (UDN) Just some bucket ideas: Lasers: $LITE, $SIVE, $COHR, LandMark (3081), LuxNet, Sumitomo, Furukawa Optical fiber / FAU: Foci, Browave, $GLW, Sumitomo Fiber Optic / CPO Connectors: BizLink, $GLW , Fujikura, Nextronics, COXOC CPO testing: MPI (6223), Advantest, $FORM, Msscorps, $KEYS, Chroma (disclosure: exposure to theme above, individual names not named by TSMC) There are others I like as well, such as ShunSin, which now has explicit TSMC COUPE exposure but probably belongs under a different category like packaging/integration. eg. "Foxconn unit ShunSin confirms TSMC COUPE partnership" I don't think there's anything too new vs. H1, aside from ongoing news (eg. FAU looks like there will have a demand imbalance in 2027, from a report last week). But it's helpful to reiterate overall beneficiaries from time to time...

Taiwan’s ‘Big 5’ chip packaging and testing firms (OSATs) will spend over NT$460 billion (US$14.4B) this year on capex in a bid to catch up with AI-related demand, media report. Industry giant ASE said its biggest problem now is how to accelerate construction, equipment installation, and capacity rollout at 13 new projects and 8 renovations: ASE: NT$335 billion (US$10.5B) Powertech: NT$50 billion KYEC: NT$50 billion Sigurd Group: NT$20 billion ChipMOS: NT$7.2 billion in the 1st half. More coming $ASML $AMAT $TER $CAMT $NVMI #BESI# #Advantest#

Japan's long-term rate touched 2.930 percent yesterday. That is the highest since September 1996. Today Tokyo gave back five sessions of gains in one. The Nikkei closed at 67,460.73, down 1,759.52 or 2.54 percent, the first fall in six sessions. Nikkei's own headline names the reason: Middle East concerns and rising rates. Two names did roughly half of it. Advantest and Tokyo Electron together accounted for about 836 of those 1,759 points, per Zaikei's contribution ranking. What was repriced is the multiple. What was not repriced is the commitment. JX Advanced Metals (TSE: 5016) decided in June to spend up to 120.0 billion yen through fiscal 2030 on InP capacity. Fuji Electric (TSE: 6504) is not raising group capex at all, it is reallocating inside a smaller number, from 85.2 billion two years ago to 56.0 billion this year. Both decisions were designed when the ten year cost of money in Japan started with a zero. This is the part the tape does not price in a single session. A multiple can move 2.54 percent in a day. A wafer line and a switchgear plant transfer are three to five year schedules with a signature already on them. So the question I am holding is narrow. Not whether Japanese suppliers are cheap after a down day. Whether any of them revises a multi-year capex plan because the discount rate moved, and which line it shows up in first. I do not think it shows up in guidance. Guidance is annual. It shows up in the capex schedule, and that is disclosed once a quarter. The September quarter closes in six weeks. Korea sits on the other side of this. SK hynix (KRX: 000660) breaks ground in Indiana on 27 August. Samsung Electronics (KRX: 005930) is expanding Pyeongtaek. Those are dollar financed. The Japanese layer under them is yen financed, and the yen curve just moved thirty years. Every capex schedule is somebody's bet that money stays cheap. That is a different risk from the one the tape traded today. I could be wrong in an obvious way: rates have been rising in Japan all year and none of these plans have changed yet. If the September filings show the same capex lines, this is noise and I will say so. Sources, in order: Nihon Keizai Shimbun, 17 August 2026, long term rate at thirty year high. Nihon Keizai Shimbun, 18 August 2026, Tokyo close. Zaikei Shimbun, 18 August 2026, Nikkei contribution ranking. Second hand. JX Advanced Metals company release, 16 June 2026. Fuji Electric FY2027 Q1 appendix. The 836 of 1,759 share is my arithmetic. My read, not advice.

Semiconductor test and metrology have become the key factor in AI chip yield, cost, performance and mass production speed, moving this formerly behind-the-scenes work to the fore, media report, citing SEMI Taiwan President Terry Tsao. Instead of just catching defects, modern test and metrology equipment now feeds real-time insights back to the design, fabrication and packaging stages for faster troubleshooting. System-Level Testing (SLT), burn-in testing, and reliability verification have all moved up in importance. #Advantest# $TER $AMAT $KLAC $ONTO $NVMI

Three companies published the same cost target. NVIDIA ($NVDA) wants co-packaged optics under 1.5 picojoules per bit. IBM ($IBM) is going for under 1. Intel ($INTC) is targeting under 5 across the package, end to end. Different numbers, because the engineering is different. Then all three name the same cost. 0.1 dollars per gigabit per second. Power targets diverge because the physics diverges. A cost target that lands on the same figure three times did not come up from the engineering. It came down from the customer. Which would be fine, except for what the customer cannot do. The director who set up Resonac's (TSE: 4004) US-JOINT consortium in Silicon Valley told Nikkei that hyperscalers and fabless companies are strong at simulation, but there are few environments where you can verify an actual semiconductor package. So the people setting the number cannot test against it. On the manufacturing side, the same week's coverage says who bears final responsibility for quality assurance is still an open question. Foundries and OSATs are not used to volume optical production, and the division of labour has not been agreed. The instruments exist. Keysight ($KEYS) announced a 220 GHz lightwave component analyzer on 12 March and showed it at OFC. The measurement is possible. The signature is not assigned. Here is why that matters more than it sounds. Both failure modes in this stack are local, not average. A fiber core and a waveguide differ in cross section by roughly 800 times, so a misalignment at nanometre scale becomes a coupling loss you cannot average away. On the thermal side a chip can run cool on average and still fail from one hot spot. Resonac buys test chips from imec that reproduce over 1000 watts and can heat a single region of the die. Testing that used to pass on averages now has to catch the local case. That means more test time per part, on parts that are already singulated. The back end already had the thinnest margins in the industry. So the layer that gets paid here is not the one making the optics. It is the one deciding whether they passed. Advantest (TSE: 6857) and Teradyne ($TER) are the duopoly in that seat. Keysight sits beside it. One more line, because the geography is odd. Resonac partnered with Purdue in May for thermal analysis. SK hynix (KRX: 000660) is putting 3.87 billion dollars into an advanced packaging site on land held by a Purdue-affiliated foundation in Indiana. A Japanese materials company and a Korean memory maker are working at the same university. Where a responsibility gap sits open, someone eventually charges a toll to close it. What would change my read: if a foundry or an OSAT publicly takes final sign-off on CPO. Then this stops being an open seat. Sources, in order: Nikkei xTECH, 17 August 2026, two articles. Keysight press release, 12 March 2026. Nikkei BP, book on optoelectronic fusion, industry map section. My read, not advice.

Spent the last few days talking with optics folks and sitting through conference talks, industry side included. As AI models advance, hardware keeps picking up more of the upside. The evidence is simple — related government and private funding programs have exploded. More funding = a bigger industry. And that naturally pulls more students into the field. Not just Korea, the US is the same story. And once the industry grows and funding ramps, equipment orders follow. But with SiPh, it's not just any equipment that ramps. The layers where an optical dimension gets added tighten first. To play the SiPh ramp, you have to know the equipment stack. Purity of the SiPh signal rises as you go down the stack. L0. Front-end fab — litho/depo/etch $ASML, $AMAT, $LRCX, $KLAC. Biggest dollars, but photonics just rides on CMOS demand. Weak as a standalone SiPh signal. L1. Wafer-level optical + electrical probing — the real bottleneck. Coupling light into the wafer while probing electrically at the same time. FormFactor $FORM (CM300 + probe card, grating-coupler alignment). Optical alignment speed is the rate-limiting step for volume ramp. L2. Parametric / metrology layer — tunable lasers, OPM, LCA, high-speed BERT/scope for EAM/modulator bandwidth. Keysight-centric $KEYS, with Viavi $VIAV/EXFO/Anritsu alongside. L3. Burn-in / KGD / reliability — $AEHR (WaferPak/FOX). Once you go CPO, you can't let a single bad optical die into a multi-chip package, so KGD becomes mandatory. L4. Packaging / final / system-level ATE — fiber attach, optical packaging, and when volume hits, $KEYS/Advantest $ATEYY/ $TER. The bottlenecks sit at L1 (optical alignment) and L3 (KGD). The moment AI forces CPO, those two layers tighten first — and once volume breaks out, the ATE above gets pulled in next.