Is it a new paradigm: compute bottleneck caused by a memory bottleneck? $AMD is raising GPU prices in response to memory component constraints, indicating that supply-side pressures are forcing the company to pass costs to customers rather than absorb them. This suggests memory availability remains a limiting factor in GPU production and that demand conditions allow price increases without losing significant market share.

$FORM : HBM and Co-Packaged Optics Double beat plus a raise.Revenue came in at $258.2M against a $240M consensus, up 31.9% YoY, and EPS printed $0.82 against $0.61. Then they guided Q3 to $260M-$280M revenue and $0.77-$0.95 EPS, both well above street. That combination alone explains most of a 16-17% after-hours move, especially since the stock had closed down 5.4% in the regular session. What actually drove the quarter: HBM and Co-Packaged Optics. Both segments, Probe Cards and Systems, grew on it. Slessor's line was that over four quarters they've grown revenue 30%+, added 1,500bp of gross margin, and tripled EPS. The advanced packaging test bet is now showing up in the P&L, not just the roadmap. The part that matters for us: CPO got named as a demand driver in a test vendor's earnings release. That's the earnings-level confirmation the CPO test thesis was waiting for.

Everyone's watching the HBM gap but I think that's not it. CXMT's HBM is captive to Huawei, a market MU is already banned from, so no TAM overlap. The threat is commodity DRAM, but the number people quote is wafer capacity roughly at 11%. By bits CXMT is roughly at 9%. Older nodes, fewer bits per wafer. Wafer share flatters the threat. And 15% isn't the scary number, it's essentially the survival number. Counterpoint calls it the threshold CXMT has to cross to fund next-gen tech, and has them at 11% in 2028. Supply storm is a 2028-29 question, not a today question.

The memory + connectivity shift OP flags is already forcing copper’s end. Scale-up fabrics hit hard limits past ~72-144 GPUs — only CPO + silicon photonics solve the bandwidth/power wall. Laser pure-plays ( $COHR, $LITE ) and $AVGO Tomahawk CPO are locking the next leg of this $550B spend.

An interesting earnings preview on $GLW, one of the data-center connectivity infrastructure companies I strongly support, with exposure spanning both inside the data center and DCI. Optical fiber and connectivity serve as the circulatory system of AI infrastructure, carrying data across increasingly large and fiber-dense computing clusters. Corning has signed a multiyear agreement worth up to $6 billion with $META, established major partnerships with $AMZN and $NVDA ( and secured two additional undisclosed hyperscaler agreements reportedly similar in size and duration to the Meta deal. The next question is no longer whether demand exists. It is how quickly these agreements translate into Optical Communications revenue, margin expansion and manufacturing capacity. Corning will report its second-quarter results before the market opens on July 28, followed by its earnings call at 8:30 a.m. ET.

A difficult market does not necessarily mean it is time to give up on AI infrastructure stocks. Share prices can decline sharply as expectations and valuations reset, even while the underlying infrastructure investment cycle remains intact. However, not every infrastructure company will benefit equally. The key question is no longer simply whether AI capital spending will continue, but which layers will capture the next wave of investment. As clusters become larger, the bottleneck is increasingly likely to shift toward memory bandwidth and capacity, intra-data-center connectivity, and DCI. The reason to remain constructive is not merely that these stocks have fallen, but that the underlying demand has not disappeared.

$GOOGL, $AMZN, $META Alphabet raised its 2026 capital expenditure outlook to $195 billion–$205 billion, while Amazon expects to invest about $200 billion and Meta plans $125 billion–$145 billion. Together, the three companies could spend as much as $550 billion, much of it on AI infrastructure. Alphabet said approximately 60% of its second-quarter technical infrastructure investment went to servers, with the remainder allocated to data centers and networking equipment. The AI buildout is therefore benefiting not only GPUs, but also power, cooling, networking, and physical infrastructure. The main risk is NVIDIA’s dependence on the capital budgets of a relatively small group of customers. Companies such as Meta continue deploying NVIDIA systems but are also expanding custom silicon developed with Broadcom and adopting AMD accelerators to reduce reliance on a single supplier. --> There is still little evidence that hyperscaler infrastructure spending is approaching an end. The more important question is no longer simply how much they are spending, but which layers of the infrastructure stack are capturing that investment. Spending on GPUs and compute systems will continue, but as AI clusters become larger, the constraint increasingly shifts from raw computation to the ability to store and move data efficiently. That makes scale-up and scale-out connectivity inside the data center, data center interconnect, and memory bandwidth and capacity increasingly important. The areas to watch now may therefore be the memory and connectivity layers that allow expanding compute capacity to be fully utilized. As long as the AI buildout continues, these layers are likely to remain critical system bottlenecks rather than optional infrastructure spending.

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Samsung Electronics and Broadcom signed an MOU covering more than $200 billion of potential cooperation through 2030 across memory, foundry and advanced packaging. The foundry collaboration covers Samsung’s 2nm-and-below processes for Broadcom products, including Wireless Broadband Communications solutions, as well as 2.3D and 2.5D advanced packaging. Samsung will also pursue HBM supply cooperation for Broadcom’s next-generation AI accelerators. The $200 billion figure is not a confirmed foundry order. It represents an estimated five-year collaboration across both memory and foundry, and the agreement is currently an MOU. --> This is clearly positive for Samsung Foundry. Securing Broadcom as a long-term partner could improve leading-edge utilization, validate Samsung’s sub-2nm process and packaging capabilities, and make it easier to attract additional AI and networking customers. At the same time, however, it should not be interpreted as a confirmed $200 billion foundry contract. The announced foundry scope explicitly includes communications and networking products such as WBC solutions, while production of Broadcom’s core custom AI accelerator compute dies at Samsung has not yet been confirmed. For now, this is a strong strategic signal imo, and the decisive catalysts will be binding purchase commitments, tape-outs, production timelines and recognized revenue, etc...

$AMD $CBRS The AMD–Cerebras partnership highlights a broader shift toward "heterogeneous" AI inference, where different processors handle different stages of the workload. AMD GPUs can manage prefill, long-context processing, and high-throughput tasks, while Cerebras accelerators focus on low-latency decoding. For memory, this supports continued HBM demand while also increasing the importance of large on-chip SRAM and tiered memory architectures. For semiconductors, it is more likely to expand the total amount of silicon per system than replace GPUs outright. In my opiniom from the context, for optics, the key takeaway is that as inference is distributed across specialized processors and racks, high-bandwidth, low-latency interconnects become increasingly important. This is not yet a direct CPO or optical-component order signal, but it is structurally positive for networking, transceivers, optical packaging, and testing. Cerebras stock gains on AMD partnership

NVIDIA's argument this week: in the agentic era, continuous post-training becomes a central compute workload, and the metric that matters is intelligence per dollar. Unpacked, that means models stop being trained once and shipped. They live inside a permanent loop of rollouts, reward checks, and weight updates. Training turns from an event into a process. And every stage of that loop moves light. Between GPUs, between racks, and between sites as updated weights ship out to serving fleets. NVIDIA wrote down why the demand keeps running. My last piece counted the physical invoice: what Korea's 8.4GW converts to in fiber strands, who actually makes the glass, and why faster transceivers do not mean less fiber. If training never stops, neither does demand for the road the light travels on. InP makes the light. Fiber carries it.

Optical networking is already widely used for scale-out connections across data centers, while low-latency scale-up links between GPUs inside a rack still rely primarily on copper technologies such as NVIDIA NVLink. As signaling speeds increase, copper links face greater attenuation, power consumption, and heat. NVIDIA plans to expand its tightly connected systems from 72 GPUs today to as many as 576 by 2027, and the company acknowledges that in-rack copper is approaching its physical limits. NVIDIA’s NVLink Fusion ecosystem now includes photonics companies such as Ayar Labs, Marvell, and Lightmatter. Ayar Labs is developing optical chiplets positioned beside processors, while Lightmatter is pursuing photonic interposers that can sit underneath compute chips. Improvements in foundry processes, hybrid bonding, packaging, and testing have made co-packaged optics more manufacturable. However, integrating large numbers of lasers efficiently and reliably remains a major challenge. NVIDIA is taking a gradual approach, adopting optics first in scale-out networks and potentially extending it into scale-up systems as bandwidth requirements increase. Industry participants expect multiple high-volume optical scale-up implementations around 2028, although this remains a forecast and copper is likely to coexist with optics for some time. --> Optical scale-up is being pursued through a wide range of architectures by multiple companies and engineering teams. Ayar Labs is developing optical chiplets, while Lightmatter is taking a photonic-interposer approach, and other implementations will continue to emerge. At this stage, predicting the eventual architectural winner is difficult. A more useful strategy is to focus on the common bottlenecks and chokepoints that every solution must pass through. As I have consistently argued, the two most critical layers in silicon photonics and co-packaged optics are packaging and measurement/testing. Optical devices, electronic chips, lasers, and fibers must be integrated with low loss, high yield, and sufficient reliability. Once assembled, both individual components and complete optical engines must also be tested at production speed and scale. As competition between architectures intensifies, these two layers are likely to determine which technologies can actually reach high-volume manufacturing.