CXMT Q3 earnings: • Net profit attributable to shareholders: RMB 53.395–54.895 billion, expected to rise approximately 1–4% QoQ—a sharp slowdown from Q2’s 113% QoQ growth. • Revenue: RMB 114.69–119.69 billion, expected to rise 15.25–20.28% QoQ. Why is net profit expected to grow by just 4% QoQ?

CXMT plans to introduce DDR5 server memory modules based on its new 4F² DRAM architecture by year-end 2026, STAR Market Daily reported on Oct. 10. The design uses vertical transistors to reduce the footprint of each memory cell. At the same feature size, it could pack more memory into a given chip area than a conventional 6F² design. CXMT did not disclose product specifications or an exact launch date, according to the report. The article also provides no yield or shipment-volume data, making it difficult to assess the scale and economics of production.

CXMT says its fifth-generation DRAM platform is now in mass production, along with two 24Gb LPDDR5X products built on it. The company says the platform has an 11.95nm half-pitch in the memory array’s active area, uses quadruple patterning, and has capacitors with a 45-to-1 aspect ratio. Analysts who initiated coverage of CXMT in late August had that generation, which they pegged at roughly 15nm class, going into mass production in H2 2028. They also had CXMT about two generations behind Samsung and Micron, with restricted EUV access as the main brake. Node class and array half-pitch are measured differently, so the 11.95nm figure does not directly map to the analysts’ 15nm classification. Their supply model counts about 300,000 wafers a month in 2026 and roughly 100,000 more each year after that. CXMT says the new platform gets more than 50% more gross die out of the same wafer at an 8Gb basis, its own figure, which would lift bit output without adding wafer starts.