.@SRamosABC reports from Pensacola Beach, FL, where conditions are rapidly deteriorating as Hurricane Isaias – now a Category 3 storm – approaches. Up to 9 feet of life-threatening storm surge is possible in parts of the Florida Panhandle, the NWS said.

Musk Targets $SPCX First SRAM Test Chip by May–June 2027, With Volume Production in H2 2028 "We're just figuring out chip fabrication. So but I'll give it I'll tell you what our internal expectations are. Which obviously I put big error bars in this, because we don't know if we will actually achieve this or not. But it's what we're aiming for internally, is to make our first sort of test chip functional in approximately May or June of next year. That's just a kind of a SRAM chip or something that basically tests the line. That's at the research fab in Austin. And we're aiming to our aspiration is to reach volume production around Q3 of '28. At Terafab, at Gibbons Creek the main Terafab location. Now, these are very aggressive dates. And we're very appreciative of ASML and all of our other suppliers in accelerating equipment deliveries in order to achieve this outcome. Let's just say that that outcome of achieving volume production is, at least in the set of possible outcomes for Q3 or Q4 of '28. So these are obviously like insanely fast time frames for chip production. We do have, I think, some significant potential breakthroughs in chip fabrication, but I don't think I should discuss that on an earnings call."

TSMC is finally set to resume SRAM scaling with its A14 node, following a stall that began after N5, according to Korean media reports. SRAM bitcell sizes have remained at 0.021 µm² for roughly eight years since the introduction of the N5 (5 nm) process in 2020. With A14, however, the size of a high-density 6T SRAM (static random-access memory) bitcell is expected to shrink to below 0.017 µm². Korean media noted that this would put TSMC ahead of Intel’s 18A process, for which Intel reported a high-density bitcell size of 0.021 µm² and a maximum SRAM macro density of 38.1 megabits/mm² at last year’s ISSCC. SRAM is the ultrafast cache memory used inside CPUs, GPUs, and AI accelerators. Smaller bitcells—the smallest individual memory cells—allow more memory to fit into the same area, directly affecting performance and power efficiency.

TeRAM Emerges from Stealth with $37M to Develop 3D SRAM for AI Systems - #semiconductordigest# #semiconductors# #semiconductor# #semiconductorindustry# #semiconductorwebsite# #semiconductormagazine#

After eight long years, TSMC is finally shrinking their 6T High Density SRAM bitcell for their A14 process! At IEDM, they will present the world's smallest bitcell, <0.017μm2 on their 2028 node. TSMC has been stuck at 0.021μm2 since N5 in 2020. With designs utilizing even more SRAM as memory bottlenecks grow, a 25% denser SRAM with A14 is significant.

$NVDA is turning MGX into a broader inference platform by adding d-Matrix Raptor for frontier models that need far more memory than SRAM can support. Groq covers ultra-fast SRAM inference while Raptor brings 2.3TB of 3D-DRAM per rack through the same NVLink ecosystem.

Groq is said to be considering using 3D stacked DRAM in next-gen chip architectures, in a possible shift away from its current SRAM-based designs as SRAM capacity is reportedly increasing just 10-20% every two years. $NVDA $MU $AMD