At a recent event at the Wushantou Reservoir in Tainan, Lai Ching-te groveled before Yoichi Hatta—a hydraulic engineer from Japan's colonial era—and brazenly claimed Taiwan must "remember the source of the water" regarding Japan. This shameless subservience is truly despicable. Any attempt to seek "independence" by courting external forces is a betrayal of the nation. Those who do so will inevitably be nailed to the pillar of shame and condemned by history. (Cartoon by Huo Xing Cheng Xiang.BCS) #TiantanView# #Taiwan# #LaiChingte# #Cartoon#

Who was there? 🙌 Airi Suzuki’s live shows in Tainan & Kuala Lumpur 🎤✨ Check the setlists here 👉 🔗 Official links: #AiriSuzuki# #JPop# #LiveShow# @airimania

UMC, Taiwan’s 2nd biggest chip foundry, has raised its capex to US$2 billion from $1.5 billion as it expands production in Singapore and Tainan, south Taiwan, media report. UMC will expand cleanroom capacity of its Phase 4 facility in Singapore and build a new fab in Tainan. Construction of the new fab is expected to take 20-months. UMC also said it plans to spend at least $5 billion over 3-years, including the $2B this year. $UMC $AMAT $ASML $LRCX $KLAC #semiconductors#

Nvidia’s next generation chip platform, Feynman is ahead of schedule, will use TSMC’s A16 process, and CPO (co-packaged optics), DigiTimes reports, with TSMC full speed ahead to meet 2028 mass production. -Nvidia is rapidly shifting its supply chain to put Feynman out in the 2nd half of 2028 -Feynman uses 3D chiplets, SoIC packaging and CPO. (Silicon-on-Integrated-Chips). -Total rack bandwidth for Feynman to hit 1,000 TB/s versus 260 TB/s for Rubin and 520 TB/s for Rubin Ultra, making CPO vital. -TSMC construction at advanced packaging plants AP7 in Chiayi and AP8 in Tainan are ahead of schedule, and accelerating -SoIC, CoWoS-L and CoPoS are all being pulled forward -SoIC capacity seen at 50,000 wafers-per-month (wpm) by end-2027, vs end-2026's 20,000wpm $NVDA $TSM #semiconductors#

UMC, Taiwan’s 2nd biggest chip foundry, is looking to expand a fab in south Taiwan due to an overflow of advanced packaging and specialty AI-related orders (silicon interposers, DTC) from Qualcomm, Intel and SanDisk, media report, noting new plans for UMC’s Fab 12A P7 near Tainan, Taiwan, are under evaluation. Orders for power management chips (PMICs) for AI products are also booming. UMC is working with Qualcomm on silicon interposers, DTC (deep trench capacitors), and wafer-to wafer hybrid bonding, while Intel and UMC have partnered on 12nm FinFET, and the UMC-SanDisk cooperation is for memory chip stacking. The story cites unnamed industry sources. $UMC $QCOM $SNDK $INTC #semiconductors#

TSMC is working hard to maintain its lead over Samsung and Intel, media report, by already preparing for 1nm production at Fab 20 in the Hsinchu Science Park with a 4-phase project (each phase is a new production line). -Fab 20 the vital sub-2nm fab. Phase 1 (P1) and P2 will do 2nm, P3 will do 2nm and A14, with room in P4 for A10 (1nm). The project is already in the hands of its R&D ‘One Team’. -Fab 18 P9 (Tainan) will do 2nm back-end and 3/5nm TSV, with equipment move-in in Q1 2027 and scale up to 25,000 wafers-per-month (wpm) -Fab 22 (Kaohsiung) main 2nm fab, 6 phases. P1 & P2 each 25,000wpm, P3 just started equipment move-in for 2nm, A16; P4 under construction, for N2, A16. -Fab 22 (STSP) P7 construction to start early-2027, will do 2nm and below processes. Has reserved space for future P8 and P9. -Fab 25 (CTSP, Taichung) will host 4-phases for A14, A13, A12 processes, with P1 already under construction, with P2 construction to begin soon, and P3 & P4 already in planning. In advanced packaging: -AP6 plant is expected to reach 10,000 wafers per month capacity by the 3rd quarter, and ramp up phase 3 for CoWoS, SoIC and InFO as well. (Hsinchu) -AP5B plant construction nearly finished, will focus on CoWoS (Taichung) -AP7 plant will be TSMC’s biggest advanced packaging campus, with P1 already packaging Apple chips with WMCM (Wafer-Level Multi-Chip Module) P2 nearly done, with equipment move-in in July, for SoIC for Nvidia. Planning for P3-P7 already underway and will support SoIC and CoPoS. (Chiayi) -AP8 will do CoWoS, with monthly capacity to exceed 40,000 wafers by end-2026, and planning for P2, P3 already started. (Tainan) $TSM $INTC $SSNLF #semiconductors# #semiconductor#

MssCorp (TWE: 6830) Serenity High Conviction Bet（analysis fully grounded in TSMC’s latest public expansion plans and 2026 industry data）： – this is the functional monopoly in CPO/SiPh inspection (90%+ share targeted, pricing power is real). Long list of customers ($TSM, $NVDA, $AAPL, $AMAT , $LRCX, $ASML , $INTC ) all need to go through them for yields. NVIDIA dedicated AI Chip Zone in US facility = strategic lock-in. -GS CPO TAM still the anchor: $91B by 2028. -TSMC CoWoS doubling to 130k-140k wafers per month by end-2026 via AP7 Chiayi (world’s largest advanced packaging hub, CoPoS pilot 2026/volume ramp 2027-28) + AP8 Tainan (P1/P2) + AP5/AP6 upgrades. We are still in the frontrunning window. Pure TSMC fab expansion model only — no NVIDIA exclusive assumed. Factory-by-factory HG demand: HG is specialized QA/FA tool (not standard per-line gear). Base Assumption~60 units per major packaging “module group” (20 front / 20 mid / 20 back). Using latest TSMC 2026 data: AP6 (Longtan/Taichung): Operating + upgrade → ~30 units / MssCorp 25-30 units AP7 Chiayi: World’s largest, CoPoS pilot → ~45-120 units / MssCorp 40-100 units AP8 Tainan (P1-P2): Construction/ramp → ~120 units/ MssCorp 100-110 units AP8 later phases + AP9: 2028+ planning → ~240-260 units / MssCorp 200-220 units TSMC only total: ~435-530 units / MssCorp 365-460 units Updated HG model (reflecting monopoly + pricing power): Industry total demand 130-200 units 26-30. With 90%+ monopoly → MssCorp ships 120-180 units (spares + repeat buys). ASP NT$60M (pricing power) + GM 60-75%. HG contribution build (NT$ bn, cumulative 2026-2030): Equipment sales + Recurring services/consumables (25–45% of equipment value over 5 years) + IP licensing (20–35% of equipment rev, 80-90% margin). Total HG contribution NT$9.5bn–NT$13bn. Core MA/FA business growing 20-30% CAGR from NT$22B 2025 base on top. Revenue path (NT$ bn): 2026: 30–38 2027: 45–62 2028: 65–88 2029-30+: 180–240/yr (normalized) Mix shifts hard to high-margin equipment + recurring + IP as CPO goes volume Share count 51.78M. With the structural monopoly in a critical yield choke-point + TSMC/NVIDIA tailwinds, long-term normalized forward EPS can realistically reach NT$180–240 (US$5.6–7.5). 40–60x forward P/E (standard for AI/SiPh leaders with real moats) → target NT$5,000+. Current MC ~$1.2–1.4B.