Taiwan Plans New Tainan Science Park to Support Future 1nm Fabs Taiwan’s National Science and Technology Council plans to begin procedures for a large new science park in Tainan in 2027, preparing for future 1nm fab construction. Council chair Wu Cheng-wen outlined the plan at the IEEE Asian Solid-State Circuits Conference on November 2, according to CNA’s report carried by Economic Daily News. The engineering significance is site readiness. A new manufacturing process needs a production location that can accommodate fab buildings, utilities and equipment before it can become usable wafer capacity. Preparing the park ahead of that investment could reduce the risk that site development delays a manufacturer’s expansion. The announcement addresses this physical prerequisite for future production. The relevant supply-chain layer is therefore fab infrastructure. Park development precedes factory construction, equipment installation and process qualification. Each stage has a different deliverable: available land enables construction; an equipped factory enables process development; qualified manufacturing enables commercial output. Starting the first stage does not establish the completion date of the others. Sources

Yes, there’s a bubble in AI. But what should semiconductor stocks be worth after it bursts? On Nov. 6, SOX traded at 13.7× forward earnings, roughly half the 25.5–28.4× observed near the 2002 dot-com bottom. Now suppose semiconductor companies earn 20% less than analysts currently forecast. If the index stays where it is, the P/E would rise to 17.1×, close to its 2011–2023 average. Meanwhile, major suppliers are still growing profits and guiding for higher revenue. Our latest publication breaks down the underlying math. $NVDA $AVGO $TSM $AMD Read the full analysis:

1/5 The expert call confirms Intel ( $INTC )EMIB-T assembly yield sits at 40.5%. While eliminating full-wafer silicon interposers cuts theoretical BOM cost by ~40% vs CoWoS-L, scrapping 60% of completed packages destroys host wafer economics. A 6x CTE mismatch between silicon bridges (2.6 ppm/°C) and organic ABF (16 ppm/°C) causes warpage during bonding. CoWoS-L retains 80%+ share through 2028.

Winbond chairman: Memory price hikes have likely peaked. Commercial Times reports that Winbond ( chairman Arthur Chiao believes memory price hikes have likely peaked. Smartphone and PC demand remains weak, and further increases could hurt consumers. Meanwhile, Winbond expects a substantial increase in output in 2027 as its capacity expansion takes effect.

Yes, Liwei is a semiconductor permabull. I’ve dug through plenty of data, and I still think today’s market pricing is a joke. If SaaS is yesterday’s business and AI is the future, explain this: five AI suppliers average just 16.8× forward earnings, while five mature software companies command 15.3×. A potentially world-changing technological revolution gets a miserable 10% premium. NVIDIA’s forward P/E is below Workday’s. Broadcom and TSMC trade below ServiceNow. If AI really is going to eat software’s lunch, and its suppliers have stronger earnings power, that tiny premium makes no sense. Of course semiconductors are cyclical. But before getting even more bearish at these levels, work out how far AI companies’ expected earnings will actually fall. Some media outlets keep shouting that “the AI bubble is bursting.” Yet I think the inflated optimism behind those bubble valuations has already been squeezed out. As retail investors, we don’t need to keep scaring ourselves.

$TSM’s Memory Rumor Blurs Three Technologies, Industry Sources Say Economic Daily cites industry sources distinguishing HBM4 logic base dies, controllers beneath future 3D DRAM, and 3DFabric/SoIC hybrid bonding. They argue these fit $TSM’s logic foundry and packaging business, without requiring it to manufacture DRAM storage arrays. True 3D DRAM vertically stacks the memory cells themselves, using 1T1C or capacitorless architectures. That introduces specialized cell structures, materials and manufacturing challenges. The sources envision $TSM supplying the underlying logic and bonding while memory makers produce the storage arrays. More involvement in memory integration therefore does not establish a move into DRAM-cell manufacturing. Sources:

According to @WSTAnalystApe data-center backlash could accelerate demand for scale-across networking. As giant campuses become harder to approve, developers could spread some capacity across smaller sites and connect them with high-bandwidth optical links. NVIDIA’s Spectrum-XGS already supports this approach. Political resistance could make it more attractive: build where power and permits are available, then link suitable sites together. Maybe that’s how you work around those anti-data-center Dem voters. They might end up making optical interconnects an even better business.

Democrats might be able to ban American superintelligence, but they can't ban China's. Do you really think an ASI trained on walled-off data will have your best interests at heart? Think again. The next generation of Americans better get ready to learn Chinese.

$INTC: Future AI packages could use at least 70 EMIB bridges Intel expects EMIB bridge counts to rise as AI packages integrate more compute chiplets and HBM stacks, according to ZDNet Korea. The packaging roadmap Commercialized in 2026: Packages up to 120 × 120 mm, with 12 HBM stacks and at least 20 EMIB bridges. Under development: Packages of at least 120 × 180 mm, with 16 or more HBM stacks and at least 38 bridges. Future configuration: A 240 × 240 mm package with at least 32 HBM stacks and 70 bridges. No commercialization date was given. Why EMIB scales differently EMIB embeds small silicon bridges in the package substrate to connect adjacent compute chiplets and HBM. This avoids the need for a large silicon interposer across the entire package. Intel says the smaller bridges can be packed more densely onto a wafer, achieving over 90% wafer utilization versus roughly 60% for large interposers. That figure measures wafer area usage, not the yield of finished packages. What EMIB-T adds EMIB-T introduces through-silicon vias and capacitors to improve power delivery and manage noise, supporting HBM4 and high-speed connections. As AI packages grow, each package could require substantially more bridges. The 70-bridge configuration is a future design, not a confirmed customer order. Intel Technical Brief:

That’s why I’ve never doubted China’s ability to improve its HBM yields quickly. And frankly, it wouldn’t surprise me if some engineers in Taiwan were willing to sell technical secrets across the strait.

MediaTek Hires Former $INTC Executive Navid Shahriari to Deepen TSMC Ties and Advance AI Chips My read is that MediaTek ($2454.TW) wants a firmer grip on packaging yields and delivery schedules. That could put more pressure on $INTC to deliver in volume. Navid Shahriari’s new responsibilities cover yields, advanced packaging, testing and reliability. If he gets involved in EMIB-T, MediaTek would have someone on its side who knows Intel’s packaging operations from the inside. He would be better placed to pinpoint whether problems lie in substrates, assembly or design integration, and push for a firm timeline to validate the fixes.

IBIDEN’s AI substrate story is about layer-area, not just chip volumes. Its roadmap moves from 90×90 substrates with 10 build-up layers per side in CY2026 to beyond 130×130 with 14 per side from CY2030 onward. Larger footprints and additional layers mean more fine-line copper wiring to fabricate per package. That explains the direction of IBIDEN’s forecast: 1.8× AI GPU/ASIC market growth, compounded by 3× production load, drives 5.4× projected SAP demand through CY2030. The key metric is qualified SAP throughput: expanding floor space alone is insufficient unless new lines deliver the required dimensions, layer counts and yields.

This is a very puzzling claim. The overall yield of EMIB cannot exceed the yield of the silicon bridge embedding process in the ABF substrate. I have seen numerous reports on EMIB yields over the years, but most have provided only fragmented information. I suspect that very few people actually have an accurate understanding of the yields at each individual process step. To the best of my knowledge, the yield of conventional EMIB (non-EMIB-T) is significantly higher than the figures cited in this report.

MediaTek: $INTC Packaging Yield Issue Identified, Rapid Improvement Expected Once Resolved MediaTek reaffirmed its Q1 2028 mass-production target for its second-generation data-center AI ASIC, which uses Intel’s EMIB-T packaging. CEO Rick Tsai said the team has identified key packaging yield issues and is working with Intel and substrate suppliers to implement fixes. He expects yields to improve rapidly once those fixes are in place. This is an encouraging sign for Intel: MediaTek continues to commit engineering resources to the EMIB-T program while maintaining its production schedule. The next milestone is demonstrating that the improvements hold across production lots as volumes increase. A successful ramp would help MediaTek meet customer demand and give Intel a concrete example of EMIB-T delivering at scale, strengthening its case with other potential AI-chip customers. H/T:@rainyang721