- Global Unichip Corp. (GUC, has announced a 16 Gbps HBM4E PHY and Controller IP on TSMC N2P, targeting next-generation AI ASICs with support for CoWoS and 3D SoIC architectures. - Importantly, the 2nm designation refers to the ASIC-side HBM PHY and Controller IP implemented on TSMC N2P, not the DRAM process used to manufacture the HBM4E memory itself. - GUC says the HBM4E PHY and Controller design has been finalized and has already been adopted by a customer's AI ASIC, although the customer has not been disclosed. - The previous 12 Gbps HBM4 PHY and Controller on TSMC N3P is already silicon-proven, with GUC now extending the platform to 16 Gbps HBM4E. - GUC CTO Igor Elkanovich says its HBM4E solution delivers 3.3x bandwidth, 2.6x area efficiency, and 1.4x power efficiency versus HBM3E, based on GUC's IP comparison. - The platform goes beyond conventional CoWoS HBM connectivity by supporting a face-up HBM PHY for TSMC SoIC-X, including TSVs for I/O, power, ground, and feedthrough power delivery to logic dies stacked above the PHY. - GUC is positioning HBM4E together with face-up UCIe and GLink-3D as a broader 3D ASIC interface platform, enabling integration across HBM, chiplets, and vertically stacked logic. - The timing is notable because SK hynix announced in June 2026 that it had shipped 12-layer HBM4E samples operating at up to 16 Gbps per pin to major customers, meaning both the memory and ASIC/IP ecosystems are now preparing for the same performance generation.