$MU $SKHY $DRAM Samsung’s SEMICON Taiwan 2026 memory roadmap. Take it with a grain of salt. These are all in R&D stage. Feasibility and specs are not guaranteed. HBM5 “the company’s HBM5 is targeting 2× the performance and 20% higher performance per watt versus HBM4E” “The performance gains will be paired with a 20% reduction in thermal resistance” Base die moving from 4nm (HBM4/HBM4E) to Samsung’s in-house 2nm node Preparing 12-, 16- and 20-layer DRAM stacks; mass production expected around 2028 zHBM “targeting 8× the performance and 3× the performance per watt of HBM4E” Aims to “reduce thermal resistance by 75%–90%” “stacks memory directly on top of the processor instead of placing memory beside the AI accelerator (xPU)” “By shortening the distance data must travel, the architecture delivers higher bandwidth and improved power efficiency” Expected launch after 2029 zNAND-O Targeted for sampling in 2028 “aims to deliver 10× the bit density of DRAM for large-scale data storage, while offering 7× the read bandwidth and power efficiency of NAND” “designed to meet the growing AI demand for DRAM-like speed and NAND-like capacity” CUBE strategy (Jangseok Choi) Four priorities: Capacity, Utilization, Bandwidth and Efficiency Capacity: expand memory vertically without enlarging PCB footprint Utilization: “3D memory as more than simply stacking layers,” optimize architecture and logic/memory placement to cut latency Bandwidth: “shorten die-to-die distances by replacing horizontal data paths with vertical high-speed channels” Efficiency: “minimizing the energy required to move each bit of data and maximizing performance per watt”