High‑NA EUV $INTC $ASML Intel proved it works in high‑volume manufacturing DRAM has the strongest economic reason to adopt High‑NA first Because DRAM scaling is hitting extreme patterning complexity: Very dense capacitor + bitline structures More EUV layers per generation Multi‑patterning costs exploding HBM4 and HBM5 require extremely tight pitches High‑NA reduces the number of EUV exposures and cuts multi‑patterning steps — saving cost. Samsung logic and TSMC will adopt High‑NA around A10 nodes (~2030). Intel is the High‑NA frontrunner in logic

From UBS They dont think china can make their EUV machine within the next 10 years I'm not an expert, but if there's one thing I know, it's never, ever underestimate China's reverse engineering capabilities $ASML

Everyday learn new things, thanks to Bernstein Global Memory: An AI memory primer TLDR: We need more CPU, GPU and memory But HBM is very import for both training and storing the model for inferencing Different workloads and hence different memory requirements: Training: Compute intensive and highly dependent on HBM bandwidth and capacity. Inferencing Prefill: Compute-bound and primarily drives TTFT (Time to First Token). Inference Decode: memory-bandwidth-bound and dominated by KV Cache access. Decode performance is often measured by TPOT (Time Per Output Token). RAG DRAM-centric because large vector indexes are commonly kept in system memory Agentic Inference demand through multiple tool calls, iterative reasoning, and repeated context injection, which can increase KV Cache usage and memory pressure and use a lot of CPU!!!

Commerce Secretary Lutnick set a goal for the US to onshore 40% of semiconductor demand by the end of Trump’s term in 2028 JPM estimate US might reach 30%-35% of advanced node production by 2028-2030 America cannot hit its semiconductor security goals without Intel $INTC