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🌿 lithos
@lithos_graphein
Three decades in semiconductor lithography. I run the Chip War Dashboard site; it's a live feed of the freshest semi news & market data.
Joined November 2022
3K Following    21.5K Followers
Here's a fresh paper on a new litho source using gadolinium. Same basic idea as mainstream EUV, but it drives a plasma with Gd instead of tin, and the multilayer mirrors use lanthanum/boron instead of molybdenum/silicon. That drops the source wavelength from 13.5 nm to 6.76 nm. Compare that resolution against today's EUV lens sizes and an introductory Gd-based system lands roughly where ASML's hyper-NA EUV is aiming. If a larger lens is even possible on top of that, you're talking about pushing into the 3 nm realm. The hard part now with introducing a new lithography tool isn't just the physics. To improve resolution, you either shorten the wavelength or increase the lens NA. Both are monumental changes, and both require standing up an entire ecosystem. That wasn't always true for NA, but in the EUV world we live today, it is. There are already process techniques that split pitch and print much smaller features without changing the scanner: self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Look at where even a large-lens Gd source sits on the scaling chart, and the raw resolution looks impressive. But a fab could still take a low-NA scanner available today and reach the same place by putting SAQP on top of it. That's also the challenge for high-NA EUV and why we see a split in philosophy between Intel and TSMC/Samsung. There are multiple ways to skin this cat. The low-NA tools already in every EUV fab can apply the same multipatterning tricks and beat high-NA resolution hands-down without taking on the ecosystem complexity of the bigger-lens tools.
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