Why did Intel abandon EMIB for their 2027 Diamond Rapids CPU? Uniform Memory Access. All CPU cores in each CBB can access all 16 memory channels with a single hop. UCIe-S through the substrate was required to route signals underneath the near-IMH to the far-IMH with about 30mm of reach to achieve this. In contrast AMD's Venice is a NUMA design. Half the memory channels are on a remote-IOD that require an extra hop for the cores in the CCD to access vs memory channels in the local-IOD. As a bonus, Intel also saves on packaging cost without having to use EMIB, freeing up advanced packaging capacity for their external foundry customers

Since people are having fun speculating on $SKHY CPO roadmap supply chains. I'm gonna do my own guess and say SK Hynix is evaluating Celestial/Ayar. Then doing heavy evaluation into microLEDs past first-gen deployments. Both have been kinda working on it for awhile. - Ayar shown up in SK hynix's own website in the context of optical <-> memory links. - Marvell is actively working with SK Hynix in custom memory solutions (and guess who owns Celestial now). Celestial/Ayar are both also cited in SK Hynix's linked Nature Paper, which helps a bit with technical relevance: (121): Stojanovic, V. A UCIe optical I/O retimer chiplet for AI scale-up. In 2025 IEEE Hot Chips 37 Symposium (HCS) 1–22 (IEEE, 2025) - This is Ayar reference (Ayar’s teraphy optical I/O chiplet), Stojanovic is Ayar Lab's co-founder btw. (123): Winterbottom, P. Photonic interconnect for accelerated computing celestial AI photonic fabric module (cough cough Celestial) There's more breadcrumbs out there, but wanted to keep this relatively short-form. For more upstream beneficaries: -> I still think $SIVE is the cleanest read through since they're likely supplying to both Celestial/Ayar. The interposer/packaging IP layer... People were speculating $POET, but Marvell probably vertically integrated players them out this year after the announcement. Given they've had their own SiPH interposer tech/integration IP before Celestials acquisition (eg. presented a silicon-photonics interposer back in 2023) -> AMS Osram (which I don't own), seems like they're co-developing in this area given they randomly went out of their way this year to say HBM <-> optics was a TAM increase for them. TLDR: I see Ayar/Celestial as candidates for SK Hynix's CPO roadmap, then microLEDs being commercialized past gen-1 maybe 2029. (this is all speculation) Just to throw a bone to quantum dot bros, this got cited like 5 times.

- Global Unichip Corp. (GUC, has announced a 16 Gbps HBM4E PHY and Controller IP on TSMC N2P, targeting next-generation AI ASICs with support for CoWoS and 3D SoIC architectures. - Importantly, the 2nm designation refers to the ASIC-side HBM PHY and Controller IP implemented on TSMC N2P, not the DRAM process used to manufacture the HBM4E memory itself. - GUC says the HBM4E PHY and Controller design has been finalized and has already been adopted by a customer's AI ASIC, although the customer has not been disclosed. - The previous 12 Gbps HBM4 PHY and Controller on TSMC N3P is already silicon-proven, with GUC now extending the platform to 16 Gbps HBM4E. - GUC CTO Igor Elkanovich says its HBM4E solution delivers 3.3x bandwidth, 2.6x area efficiency, and 1.4x power efficiency versus HBM3E, based on GUC's IP comparison. - The platform goes beyond conventional CoWoS HBM connectivity by supporting a face-up HBM PHY for TSMC SoIC-X, including TSVs for I/O, power, ground, and feedthrough power delivery to logic dies stacked above the PHY. - GUC is positioning HBM4E together with face-up UCIe and GLink-3D as a broader 3D ASIC interface platform, enabling integration across HBM, chiplets, and vertically stacked logic. - The timing is notable because SK hynix announced in June 2026 that it had shipped 12-layer HBM4E samples operating at up to 16 Gbps per pin to major customers, meaning both the memory and ASIC/IP ecosystems are now preparing for the same performance generation.

Samsung's custom HBM talk is great. Building a base die on leading edge node affords the following advantages: 1) The TSV PHY block gets smaller enabling more parallel TSVs 2) The D2D PHY gets smaller which means that silicon area on both the base die and the XPU gets smaller. This opens up space on XPU and base die for other functions. 3) The memory controller usually on the XPU die, can be integrated on the base die. 4) Advanced RAS functions will be integrated into the base die. Thermal, voltage, process, and aging sensors enable real-time, high-speed telemetry. The SRAM on advanced base die can be used to perform repair and correction. 5) The custom die will incorporate more proessing elements bringing some level of compute to the base die. 6) The extra space can also be used for memory extension controller so that expansions to things like HBF are possible. 7) Eventually, the plan is to stack the custom base die + hbm stack (more like 4 high due to thermals) on top of compute --> zHBM. The main thermal problem comes from D2D block, but vertical stacking means that the D2D will be more distributed (edge vs area) thereby helping thermals. 8) Samsung prefers the use of proprietary D2D, rather than UCIe because they feel UCIe is larger, and not quite energy efficienct.