Photon Capital(@PhotonCap):I think the answer would be both. Easier to engineer, harder to supply.Easier because designers can now place each byte in the cheapest memory that meets its latency budget. That relieves the scarcest tier, HBM.Harder because demand doesn't shrink, it just spreads across tiers sharing the same fab capacity. Helios is the proof: AMD planned 1TB of LPDDR per GPU as a relief valve, then deleted it because that memory got tight too. Shortages leak across tiers. And the hidden tax: once memory splits into pools, the wires between pools become the new bill.

2026.07.27 04:21

I think the answer would be both. Easier to engineer, harder to supply.Easier because designers can now place each byte in the cheapest memory that meets its latency budget. That relieves the scarcest tier, HBM.Harder because demand doesn't shrink, it just spreads across tiers sharing the same fab capacity. Helios is the proof: AMD planned 1TB of LPDDR per GPU as a relief valve, then deleted it because that memory got tight too. Shortages leak across tiers. And the hidden tax: once memory splits into pools, the wires between pools become the new bill.