I cross-checked the two papers Culper cites on $CBRS power draw. The numbers line up with the figures, but the papers describe measurement boundaries and operating conditions more carefully than the surrounding narrative. "Jacquemin et al. 2022 (CS-2)": The quoted 16.1 kW baseline and 22.9 kW peak are correct. Baseline is whole-chassis power (pumps, fans, power-supply losses, I/O), not the wafer alone. Coolant temperature only rose from 23.6 °C to 25.6 °C during the run, consistent with tightly managed thermals. "Golden et al. 2026 (CS-3, Llama-3.1-8B)": Idle power is shown near 80 % of TDP, and both prefill and decode run close to 100 % of TDP. Other systems in the same figure (H100, A100, MI300, Gaudi, SambaNova) sit lower during decode (roughly 45–80 %) and show lower idle. Measurement boundaries differ between board-level tools and wall power, so direct percentage comparisons need that context. From a chip designer’s perspective: large temperature swings create additional mechanical stress on a wafer-scale die and its package connections. Maintaining a more constant background load to limit thermal cycling is a reasonable option under those physical constraints. Operating at low junction temperature with cold coolant is also a different regime from the high-temperature qualification conditions typically used for wear-out lifetime estimates. The practical question is therefore economic: how the extra energy cost of a near-constant load compares with any reliability or lifetime benefit it provides. That balance depends on actual utilization. At high utilization the idle contribution becomes a smaller fraction of total energy; at lower utilization it has a larger effect on total cost of ownership. Fleet-level failure and replacement data would help quantify the trade-off. Not investment advice. Just trying to separate the engineering details from the narrative. $CBRS