📈 Roth IRA too. It’s so simple. Only one ETF, $DRAM, is in my Roth IRA account now. In addition to my ordinary brokerage, the Roth IRA is also all green today. 💚 Of course, the other accounts are the same. Happy green! 💚

X’s Original Content Rewards (OCR) application asks you to pick 10 originals from a short window. I built a helper for that. Original 10 - Enter a public handle. It scores your posts against X’s originality rules and proposes the 10 to submit. How to use is in the comment. 👇

I’m excited to launch the official Substack at under @SVTrivo Second deep-dive is up — a retouched and updated version of my earlier piece: 'Why They Could No Longer Rely on NVIDIA GPUs Alone' 📌 Read the 2nd post: 7-day free Subscription is activated! #SVTrivo# #Substack#

Thanks @PhotonCap for writing this up so carefully. Photonics is still a new area for me, so I can’t claim I followed every layer — but pieces like this are how I’m starting to learn it. Appreciate the work.

SK hynix’s Nature Electronics CPO paper isn’t a product schedule — it’s a positioning signal. All three memory makers are already on the same interconnect company’s cap table. Sharp read by @PhotonCap

The person who presented for Samsung is someone who moved from Samsung S.LSI to the memory side as an HBM “relief pitcher.” He came to present at Hot Chips today, but I had other schedules so I couldn’t meet him in person—I only touched with him yesterday in advance. He has cleared one hurdle and is now pushing zHBM as the next stage. Three-step evolutionary roadmap: Phase #1# (offloading & optimization): reclaims xPU silicon area by adopting compact D2D PHYs and offloading memory controllers to the B-die. Phase #2# (functional expansion): integrates value-added logic—such as telemetry sensors, external memory expansion, and PEs—directly into the B-die. Phase #3# (true 3D convergence): eliminates 2D/2.5D interfaces via zHBM, achieving direct vertical integration of xPU logic and DRAM stacks for maximum energy efficiency. Big thanks to Tae Kim (@firstadopter) for posting the photos live from the venue—those shots let us clearly see the actual slides. From the slides: - The industry is rapidly moving toward tightly coupled AI memory solutions. The key challenge for AGI and inference is maximizing tokens per second within strict power limits. zHBM is presented as the ultimate solution: true 3D vertical integration of the xPU and C-die stack that completely eliminates the 2.5D interposer. - Key differentiators of zHBM are distributed I/Os and a true 3D structure. Distributed I/Os minimize data travel distance inside the stack, the 3D structure removes conventional 2D interfaces (HBM PHY or D2D), and the design targets ultra-low power consumption. - The primary advantage is a dramatic reduction in I/O power. By removing SERDES (data align/DQ I/O) overhead, zHBM delivers about 70% lower power versus HBM5. At the system level (1× GPU + 4× memory stacks, assuming 1200 W GPU), this translates into roughly 230% higher DRAM bandwidth, a ~100 W saving, and an 8.3% improvement in overall power efficiency.

$SMCI just dropped unholy FY2027 guidance: $65–72B revenue vs ~$52B consensus, plus $60B+ in new orders, and the xAI/SpaceX DC timeline from June is looking real. But after the repeated integrity issues — including the $2.5B China diversion scheme with dummy servers and hair-dryer label swaps — a lot of us who dug into the details on the ground decided we’d rather make money elsewhere. I posted what I learned directly from local contacts right after the FBI raids here: Numbers can be packaged. Trust is harder to rebuild. Investment is always personal — I’m just keeping my distance.

Yeah… Anthropic just casually dropping $500–850k for a Research Engineer, Chip Design RL role. Looking at the requirements — full ASIC/FPGA flow, RTL to tape-out, UVM/formal, physical design, PPA, DFT, EDA tools, balancing research with actual silicon delivery… These are just the things I’ve been doing for years. Nice. Sometimes it’s just fun to see what compensation bands and roles these companies are putting out.

SILITH and UMC Achieve Mass Production Milestone for Silicon Photonics. - UMC is the 2nd largest foundry in Taiwan after TSMC. - SILITH Technology is a Singapore-headquartered silicon photonics company developing next-generation photonic integrated circuit (PIC) solutions for AI infrastructure and high-speed optical networking.