Semiconductor Engineering
@SemiEngineering
Deep Insights For The Tech Industry
#semiconductor# #semiEDA# #AI# #embedded# #verification# #lowpower# #test# #DataAnalytics# #automotive# #chipdesign# #ICmanufacturing#
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Larger packages, finer routing, and embedded functions are pushing advanced substrates toward application-specific designs.
#semiconductor# #substrates# #advancedpackaging# #GlassSubstrates#
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As AI chips move to stacked, chiplet-based architectures, EDA vendors are reworking mature tools for cross-domain analysis, faster exploration, and agentic AI assistance.
#semiconductor# #semiEDA# #3DIC# #AgenticAI# #chiplets#
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Latest: AI agents move deeper into chip design; China doubles down on AI compute/memory; supply chains tighten; TSMC partners accelerate; ICs head to space; optics advances, neural super resolution, auto PQC; Purdue-UIUC workforce training
#semiconductor#
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Redundant feeds protect uptime, but they also strand capacity that could support more hardware.
Thermally induced warpage, caused by differences in the rate at which materials expand when heated, is becoming problematic in large chips/packages.
#semiconductor# #warpage# #NTE# #CTE#
@mcgc_en @AmkorTechnology @brewerscience
#advancedpackging# @Synopsys
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Latest: AI agents move deeper into chip design; China doubles down on AI compute/memory; supply chains tighten; TSMC partners accelerate; ICs head to space; optics advances, neural super resolution, auto PQC; Purdue-UIUC workforce training
#semiconductor#
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New technical papers recently added to Semiconductor Engineering’s library
#semiconductor# #3DIC# #chiplets# #BEOL# #thermalmodeling# #semiEDA# #neuromorphiccomputing# #LLMs#
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Specialization and orchestration are becoming more important as the role of AI agents in chip design widens, but coordination, control, and trust remain challenging
#semiEDA# #AgenticAI# #chipdesign# #semiconductor#
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The difficulty in building a package digital twin goes beyond creating accurate electrical, thermal, or mechanical models.
#semiconductor# #advancedpackaging# #digitaltwins# #chiplets# #semiocnductormanufacturing#
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Robotics and AI are taking on more tasks in fabs today, particularly to reduce unscheduled downtime and ensure more good wafers are produced with existing capacity.
#semiconductor# #fabs# #robotics#
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Thermally induced warpage, caused by differences in the rate at which materials expand when heated, is becoming problematic in large chips/packages.
#semiconductor# #warpage# #NTE# #CTE#
@mcgc_en @AmkorTechnology @brewerscience
#advancedpackging# @Synopsys
Show more
New technical papers recently added to Semiconductor Engineering’s library
#semiconductor# #3DIC# #chiplets# #BEOL# #thermalmodeling# #semiEDA# #neuromorphiccomputing# #LLMs#
Show more
Robotics and AI are taking on more tasks in fabs today, particularly to reduce unscheduled downtime and ensure more good wafers are produced with existing capacity.
#semiconductor# #fabs# #robotics#
Show more
Latest: Major memory deal; AI Infra Summit news; US chip capacity plans; 2nm & below advances; Huawei’s chip offensive; Chinese equipment makers gain share; India’s chip build-out; McKinsey’s tech trends; major funding rounds..
#semiconductor# #tech# #2nm#
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Rising power density and chiplet complexity drive thermal considerations earlier in the design process.
#thermal# #datacenters# #multiphysics# #advancedpackaging# #3DIC# #semiconductor#
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Latest: Major memory deal; AI Infra Summit news; US chip capacity plans; 2nm & below advances; Huawei’s chip offensive; Chinese equipment makers gain share; India’s chip build-out; McKinsey’s tech trends; major funding rounds..
#semiconductor# #tech# #2nm#
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The difficulty in building a package digital twin goes beyond creating accurate electrical, thermal, or mechanical models.
#semiconductor# #advancedpackaging# #digitaltwins# #chiplets# #semiocnductormanufacturing#
Show more
Discrete steps are being merged with others as dimensions shrink into the angstrom range.
#semiconductor# #2nm# #Sub2nm#
Redundant feeds protect uptime, but they also strand capacity that could support more hardware.
Rising power density and chiplet complexity drive thermal considerations earlier in the design process.
#thermal# #datacenters# #multiphysics# #advancedpackaging# #3DIC# #semiconductor#
Show more
