Thermally induced warpage, caused by differences in the rate at which materials expand when heated, is becoming problematic in large chips/packages. #semiconductor# #warpage# #NTE# #CTE# @mcgc_en @AmkorTechnology @brewerscience #advancedpackging# @Synopsys

Taiwan Leads the FOPLP Race, Production Ramps Up Taiwan currently leads FOPLP, with PTI, $ASX and Innolux already in production · PTI: 510 × 515 mm · ASE: 310 × 310 mm · Innolux: 620 × 750 mm · TSMC: CoPoS pilot line, with mass production targeted for 2028 The main technical constraint is warpage and yield at larger panel sizes. Companies are using RDL stress balancing, CTE matching and stress-control films Innolux demonstrated a 10-layer RDL sample without warpage The longer-term shift is from glass as a temporary carrier to glass-core substrates with TGVs, creating demand for TGV drilling, metallization, inspection, handling and automation equipment · Intel: Started glass development early but faces a more complex process and glass-breakage challenges · Samsung: Using 415 × 510 mm panels and plans to outsource TGV glass. Mass production before 2030 appears unlikely · Japan: Rapidus targets 600 × 600 mm glass packaging in 2028, while AOI Electronics and Sharp are also developing glass packaging

Samsung (005930.KS) challenges $TSM production with Panel-Level-Packaging Samsung plans to bring its 415×510mm FOPLP platform into mass production around 2028, sticking with a significantly larger panel format than TSMC’s 310×310mm standard The larger Samsung panel offers 2.2× the usable area of a 310×310mm panel, potentially providing meaningful unit-cost advantages. Samsung also already has high-volume PLP manufacturing experience from mobile and wearable chips, giving it existing infrastructure and expertise in warpage control The challenge is moving the technology into AI server packaging, where integrating logic dies and HBM is considerably more difficult. TSMC also has an established advantage because its 310×310mm format has already attracted a large equipment, materials and OSAT ecosystem Samsung is also targeting glass-substrate mass production in 2029–2030 as package sizes increase and conventional ABF substrates face growing technical and supply constraints Perhaps most interestingly, Samsung is aggressively using AI in packaging R&D. Physics-Informed Neural Networks are being applied to signal integrity, power integrity and thermal simulations, reportedly reducing some engineering workflows from one year to a single day

Nvidia got FAFOed multiple times with Rubin/Rubin Ultra design - They pushed for higher pin speed HBM4, but Micron's & Hynix's base die were subpar, so they had to change plans & face delays (lower pin speeds) - They pushed for a quad die Rubin Ultra design, yield and warpage issues forced them to switch to 2 die and 2+2 die MCM design - They pushed for 16 Hi HBM4E for Ultra, yield issues forced them to come back down to 12 Hi - They pushed for a dual profile 2.3kW/1.8kW Rubin, but indium-graphite TIM was unstable and now they are switching back to graphite TIM

"Three out of four are defective"... China's CXMT struggles with HBM yields, with immature TSV technology to blame ChangXin Memory Technologies (CXMT), China's largest DRAM maker, has begun trial production of fourth generation high bandwidth memory (HBM3), but initial yields are barely improving. Yields are reported to have stalled at 25%, roughly one third of the so called "golden yield" of 80% that the semiconductor industry treats as the threshold for volume production. The gap is stark compared with SK hynix, which has been mass producing the same product since 2022 and has secured yields above 90%. Industry sources point to the gap in maturity of through-silicon via (TSV) technology, the core process for stacking and connecting multiple DRAM layers, as the root cause. ◇ "DRAM has caught up, but HBM stacking is a different problem" According to a senior official at a semiconductor equipment company familiar with CXMT's situation on the 9th, the yield of CXMT's HBM3 8-High product is stuck at around 30% in the front end process. Of the products that survive that stage, only about 70% are recognized as final good units after passing through the back end process. In simple terms, if 100 HBM3 units are started, close to 80 of them fail the final test. CXMT is reported to be supplying the small volumes of HBM samples it produces this way to Chinese companies such as Alibaba's T-Head and Cambricon while continuing its yield improvement work. The problem is that the issue does not lie in the fine process technology of the DRAM itself. A semiconductor equipment industry official explained, "There is no major problem with the standard DRAM that CXMT makes on its 'G4' (17nm class) process used for HBM. However, the DRAM dies used for HBM are larger in area than standard products and have more demanding electrical specifications, so even on the same process they are much harder to pass the acceptance criteria." In other words, CXMT's fundamental capability in making standard DRAM has risen to a considerable level, but a bottleneck is emerging at the stage of converting it into the high performance product that is HBM. At the heart of that bottleneck, according to industry sources, is the TSV process. ◇ The real hurdle is TSV... "Impossible to catch up without years of accumulated know how" TSV stands for "Through Silicon Via" and refers to the microscopic copper wiring that passes vertically through each layer to carry electrical signals when DRAM is stacked in multiple layers, as in HBM. It is a highly demanding process in which a DRAM wafer is thinned down to several tens of micrometers, a fraction of the thickness of a human hair, after which thousands of tiny holes are drilled through that thin silicon plate and filled completely with copper. A single hole that is misaligned or not properly filled can cause the entire layer to be rejected, making it one of the semiconductor processes with the most stringent precision requirements. The consensus in the industry is that this is the process where the technology gap between CXMT and the leading companies is widest. According to analysis by semiconductor research firm Nomad Semi, Samsung Electronics' HBM2 (second generation HBM) has more than 5,000 TSVs per die and SK hynix's HBM3 has more than 8,000, while CXMT's is understood to have only around 3,000. A smaller number of TSVs means sacrificing bandwidth (data processing speed) in exchange for lower process difficulty, yet even so CXMT's yields still fall far short of Samsung and SK hynix. TSV is a process that is challenging even for the industry leader: SK hynix itself publicly disclosed in 2024 that the yield of the standalone TSV process was only 40 to 60% at the time. On top of this, yield losses also occur in the back end (stacking and bonding) stage where the dies are actually stacked and joined. If even one of the eight dies is misaligned, if a microscopic void forms at a bonding interface, or if a layer warps during the thermocompression bonding process (warpage), the entire stack is scrapped. Because the number of possible failure points grows with each additional layer, the difficulty rises exponentially. Given that CXMT is already showing such poor yields at 8-High, some expect it to face even greater difficulties when moving to higher stacks such as 12-High. A semiconductor industry official explained, "The TSV process is an area that only stabilizes after years of accumulated wafer handling know how. Chinese companies have rapidly closed the gap in the fine process technology of DRAM itself, but back end know how such as TSV and bonding is difficult to catch up on in a short period." He added, "That said, Samsung Electronics also had initial HBM4 (sixth generation HBM) production yields below 60% in February this year and raised them to 80% within six months, so it is too early to declare CXMT's 25% yield a 'failure.'"

🧠 Hot Chips 2026: AI's Memory Wall Is Becoming a Money and Packaging Wall Hot Chips 2026 is still producing the usual charts of larger chips and higher peak compute. But this year, memory vendors are becoming central to the AI hardware story. The reason is simple: adding more arithmetic is getting easier. Keeping those units fed is not. Zhihu contributor 乱序摸鱼 reviewed the conference's memory talks and traced a larger shift across Samsung, Micron, SK hynix, and emerging architectures such as HBF. His main takeaway: the boundary between compute and memory is starting to dissolve. 1️⃣ The Memory Wall has become a Money Wall AI is not merely consuming more memory. It is pushing the DRAM industry toward a far more silicon-intensive product. For the same capacity, HBM requires roughly 3× the DRAM die area of DDR. A wafer redirected to HBM can therefore deliver fewer total bits, even before packaging and yield are considered. At the same time, new DRAM capacity can take more than two years to become productive. AI accelerator demand changes much faster. The article cites a revealing mismatch: AI compute can grow around 3× every two years, while HBM bandwidth grows by less than 2× over the same period. HBM solves the bandwidth problem through massive parallelism: wider interfaces, more channels, more banks, TSVs, and advanced packaging. But the bandwidth is not free. Its cost appears elsewhere as silicon area, power, packaging complexity, and yield risk. 2️⃣ The HBM base die is turning into a SoC Traditional HBM had a clean division of labor. The upper DRAM dies stored data, while the base die handled interfaces, testing, and basic routing. HBM4 changes the economics. Once the base die moves to an advanced logic process, using it as an expensive wiring layer becomes increasingly difficult to justify. Samsung's roadmap therefore expands its role in stages. The shorter-distance PHY comes first. Then the memory controller moves down from the xPU, followed by telemetry, repair, testing, RAS, and potentially lightweight processing. This turns HBM from a passive device into something that understands its own banks, temperature, failure state, and access scheduling. But integration creates new tradeoffs. A shorter interface may reduce energy per bit while concentrating the same throughput into a smaller area, raising local power density and creating thermal hotspots. The base die is becoming smarter, but every new function brings more RTL, validation, thermal design, and software work. 3️⃣ Near-memory compute should be measured in bits avoided Putting compute near memory sounds attractive, but available silicon is not enough to justify doing it. The more useful question is: How much data movement disappears after this operator moves closer to memory? Filtering, compression, copying, search, and simple reductions can make sense near memory. They may scan a large dataset and return only a small result, eliminating enormous amounts of traffic. Dense matrix multiplication is different. Data moved into a GPU may be reused many times by Tensor Cores. Moving that computation into a constrained base die could create a weaker accelerator while adding a new compiler and runtime target. The author's rule is practical: move operations that significantly reduce data volume, not operations that merely fit into spare logic area. Samsung's zHBM takes this idea further by vertically stacking HBM above the xPU. The modeled design removes much of the millimeter-scale horizontal path between memory and compute. Samsung's public targets suggest around 70% lower I/O power and roughly 100 W saved in a modeled 1,200 W GPU system. Those are architectural targets rather than proven production results. The shorter electrical path also introduces harder problems in bonding yield, thermal design, power delivery, repair, and cross-die ownership. 4️⃣ HBF could add a cold tier, but software must make it work High Bandwidth Flash proposes another route: use stacked NAND to provide much more capacity at a lower cost than HBM. The tradeoff is severe. HBF may offer cheap capacity, but its bandwidth per gigabyte is roughly an order of magnitude lower. That makes it unsuitable as a drop-in replacement for HBM. Its strongest use cases are large datasets with consistently low access rates: 🔹 Cold MoE experts 🔹 Sparse KV cache 🔹 Prefix cache 🔹 Model state that must remain nearby but is not read every token Even MoE is not automatically a good fit. A single token activates few experts, but a larger batch combines expert requests from many users. The supposedly cold expert pool can become hot surprisingly quickly. The harder problem is system software. An HBM-HBF hierarchy needs placement, allocation, prefetching, request coalescing, cache policy, wear management, and runtime telemetry. The article's verdict is cautious: the architectural need is real, but HBF's path from an attractive model to a dependable product remains largely unproven. 5️⃣ HBM scaling is becoming a packaging problem SK hynix's presentation shows why adding more DRAM layers is no longer a simple capacity upgrade. Moving from 12Hi to 16Hi increases the number of layers by 33%, while the package height rises from roughly 720 μm to 775 μm, an increase of less than 8%. The remaining option is to compress everything. Dies become thinner, inter-die gaps narrower, and bump pitches denser. Warpage, underfill, thermal resistance, and bonding yield all become harder to control. Yield is also cumulative. A defect introduced early may only appear after many expensive processing and stacking steps have already been completed. For 20Hi and beyond, hybrid bonding becomes less of a futuristic option and more of a practical necessity. By removing conventional bumps and thick underfill gaps, hybrid bonding can reduce interconnect pitch and thermal resistance. It can also return part of the height budget to the DRAM itself. SK hynix estimates that, within the same overall stack height, core dies could be up to 24% thicker than with MR-MUF while using an interconnect pitch below 18 μm. That extra silicon thickness matters for mechanical strength, wafer handling, warpage, and manufacturability. 6️⃣ The real boundary being redesigned The most important Hot Chips 2026 memory story is not another increase in TB/s. It is the rising cost of the physical distance between data and compute. As arithmetic moves from FP16 to FP8 and FP4, chips can contain more MAC units than the system can consistently feed. Performance is increasingly lost to memory access, synchronization, interconnect power, thermal limits, and data placement. The optimization target is therefore expanding from one chip to the entire task path. HBM base dies are becoming logic devices. Memory controllers are moving closer to DRAM. Flash may become another managed AI memory tier. Compute and memory may eventually be vertically integrated. None of this eliminates complexity. It decides where that complexity should live so the whole system becomes more efficient. The author's final insight is a good one: Sometimes the best architecture does not make the road faster. It discovers that the trip never needed to happen. 🔗 Full analysis: #HotChips2026# #HBM# #AIInfrastructure# #Semiconductors# #MemorySystems# #AdvancedPackaging# #AIHardware#