New technical papers recently added to Semiconductor Engineering’s library #semiconductor# #3DIC# #chiplets# #BEOL# #thermalmodeling# #semiEDA# #neuromorphiccomputing# #LLMs#

As AI chips move to stacked, chiplet-based architectures, EDA vendors are reworking mature tools for cross-domain analysis, faster exploration, and agentic AI assistance. #semiconductor# #semiEDA# #3DIC# #AgenticAI# #chiplets#

Rising power density and chiplet complexity drive thermal considerations earlier in the design process. #thermal# #datacenters# #multiphysics# #advancedpackaging# #3DIC# #semiconductor#

$MU $SKHY $TSM Custom ASICs matter more every year, and this year's SEMICON Taiwan makes the case louder than usual. Reportedly, CSPs aren't just attending anymore, they're the ones driving spec direction. Custom = Not Interchangeable. SEMICON Taiwan 2026: Highlights Global exhibitors: over 1,300 companies, 4,300 booths, drawing 65 countries and over 100,000 professionals National pavilions surged 250%, with 18 countries setting up 220 booths Cross sector collaboration: first ever partnership with Taiwan High Speed Rail linking semiconductors and transportation infrastructure CSP giants converge, full chain vertical integration Downstream customers and cloud service providers (CSPs like Google, Microsoft, NVIDIA, AMD, MediaTek, Foxconn) are driving spec direction Google's SVP of AI and Infrastructure, Amin Vahdat, delivers his first public keynote in Asia The semiconductor show and COMPUTEX's system side boundaries are increasingly merging, building an integrated ecosystem platform Startup momentum and capital access doubling 16 top startup teams featured, spanning advanced process, AI, silicon photonics, and test/measurement/quantum First time dedicated zones: "Chip Startup Stage" and "Innovation Investment Day" plus ecosystem partner events, accelerating commercialization and capital matching Frontier tech and new specialty zones debut AI advanced packaging: focus on 3DIC, CoWoS, FOPLP Silicon photonics (SiPh) and CPO: aligned with TSMC's production timeline, co packaged optics positioned as the core solution to CSP data center bandwidth and power walls Quantum technology zone Wafer smart manufacturing zone Sustainability and edge applications: SiC/GaN compound semiconductors and green process showcased

$MU $SKHY $DRAM $NVDA $LITE AI is still diapers According to $TSM's HPC roadmap (SEMI Taiwan today), AI compute demand growing 5x/year, creating a "compute wall" and "memory bandwidth wall." TSMC's answer is heterogeneous integration across logic, 3D packaging, and silicon photonics. Logic process: Moving fully to nanosheet architecture. After N2 and A16, TSMC targets A14 (angstrom class) in 2028 to 2029. 3D stacking (SoIC): In production since 2023 with 56x the interconnect density of traditional 2.5D. Roadmap is N2P on N3P in 2026, then A14 on A14 in 2029, shrinking bump pitch to 4.5 microns. CoWoS packaging: 5.5x reticle size in 2026 (supporting 12 HBM3E/4 stacks, yield over 98%), 9.5x reticle by 2028, and over 14x reticle with 24 HBM stacks by 2029. Combined system compute: TSMC projects SoIC plus CoWoS integration will deliver 50x the 2024 compute level by 2029. HBM4 and the memory wall: Interface bandwidth doubles to 2048 bit. Base die built on N12, cutting power over 45% and boosting bandwidth 2.5x, with a future move to N3 for further gains. Overall memory bandwidth is projected to grow 34.6x by 2029. COUPE (silicon photonics): 3D stacks the electronic die directly onto the photonic die via SoIC, with 2 to 4 micron bond pitch. At 112Gbps, transmission loss is just 0.06dB versus 1.38dB for microbumps, cutting latency to 10 to 20 nanoseconds. First 200Gbps micro-ring modulator (0.5 Tbps/mm density) ships in 2026, scaling to 4 Tbps/mm by 2030. Design enablement: TSMC is building an optical PDK for electro-optic co-simulation plus automated DRC/LVS/thermal flows to speed 3D IC and photonic design.

Powertech ( emerges as a key advanced-packaging supplier for $AMD and $AVGO AMD and Broadcom have already booked most of Powertech’s planned FOPLP capacity, with mass production expected to begin by mid-2027. Capacity is projected to increase from 1,000 panels/month in 2026 to 2,000 by mid-2027 and 5,000 in 2028 Powertech expects total investment in the platform to reach NT$70B, while the initial pilot-line investment is expected to break even in 2027. Management expects FOPLP to become a major growth driver from 2027 onward Its PiFO platform uses panel-level RDL and silicon bridges to connect SoCs, ASICs, HBM and chiplets. Powertech says yields have already surpassed 90%, with a longer-term target of 95–99% Beyond FOPLP, Powertech is also expanding into TSV/3D IC stacking and optical engines/CPO, giving the company exposure to several of the fastest-growing areas of AI semiconductor packaging

Marvell $MRVL could pick up the memory I/O work in Google’s $GOOGL TPU v10. Morgan Stanley still expects Broadcom $AVGO and MediaTek 2454 TT to keep the core TPU design roles. In the bank’s model, Google owns the compute die and photomasks. MediaTek designs the electrical I/O die and integrates the compute die, I/O die and HBM using Intel’s $INTC EMIB-T packaging. Global Unichip 3443 TT or another design house could handle 3D IC and CPO. TPU v10 could move to 3.5D packaging and expand beyond 12 reticle equivalents, compared with roughly nine today. Even without revenue from the compute die, Morgan Stanley estimates MediaTek could book about $18,000 per TPU v10, up from $13,000 on v9. The bank models 4 million v9 units and 1 million v10 units in 2029, putting MediaTek’s TPU revenue at around $70 billion.