Memory bandwidth has been the limiting factor for LLM inference for a while now, and anyone building out inference capacity is paying for it in power and in cost per token. @Qualcomm has been talking about High Bandwidth Compute as its answer to that problem, and today it showed first-generation HBC silicon working in its San Diego lab, running the full memory read-write path and near-memory compute at production-representative sizes. The numbers Qualcomm is sharing are big, with 18x the effective bandwidth of LPDDR5X and more than 5x the bandwidth per watt of HBM4. Those are Qualcomm estimates, normalized from ATE testing and compared against published competitor specs, so I'll want to see how they translate once HBC is sitting inside a full accelerator. That first accelerator will likely be Dragonfly AI250, which Qualcomm expects to sample in the first half of 2027 as part of its Dragonfly Rack platform. A data center product has already taped out and early bring-up of the bonded DRAM stack is apparently yielding well, which tells me this has moved past the research phase. Qualcomm has more than a decade of experience bonding DRAM onto logic from its mobile business, but HBC is the first time I've seen that work pointed directly at data center inference economics. If HBC delivers anything close to those efficiency numbers in a shipping system, the market impact could be significant. HBM supply has been one of the tightest constraints on AI infrastructure buildouts, and it is a big part of what makes today's accelerators (and basically everything else!) so expensive. An inference platform that gets its bandwidth from a different memory approach would give hyperscalers and cloud providers another lever on cost and supply, and it would put real pressure on NVIDIA and AMD in the inference tier, where tokens per dollar per watt matter more than peak training performance. Silicon is only part of what these customers are buying, though. Hyperscalers commit to a platform for years, and they need confidence in a multi-generation roadmap, a mature software stack, supply they can count on and support when things break at scale. Qualcomm walked away from its Centriq server CPU effort in 2018, and data center buyers have long memories. The HBC results are a strong technical step, and the next couple of years will determine whether Qualcomm can prove it is the kind of reliable, long-term partner these companies need.

AMD has followed up its Advancing AI data release with a new blog and a white paper on EPYC Venice that attempts to put real detail behind the claims first made on stage in July. The 2.24x platform and 1.2x per-core advantages over NVIDIA Vera in SPECrate 2026 Integer now come with estimated scores, compiler versions, memory configurations, and all 14 subtests broken out. The generational data is impressive, with the 256-core EPYC 9996 landing between roughly 1.5x and 1.8x over the 192-core Turin flagship across Redis, NGINX, MySQL, MongoDB, and server-side Java, all measured by AMD on Venice silicon. @AMD also rebuilt its 100 kW rack model around SPEC CPU 2026, which moved Venice to 3.4x over Vera and nudged its own Turin figure down slightly. The core story is the same one AMD told at Advancing AI, now with some supporting detail. The agents-per-watt and performance-per-watt claims from the keynote have no backing data in this paper, interestingly. All of it is AMD internal testing or estimates, so independent results on shipping systems from both vendors are what will settle the debate. Blog: White paper:

During the @NVIDIA Q&A with Jensen I had the chance to ask the final question: "With the PC market being low margin and cut throat, why enter it now?" His answer was compelling. He dismisses margin concerns and focuses on the opportunity to add value and reinvent what we love.