Google’s TPU v9 could use fewer PCB layers than Amazon’s Trainium 4 while requiring more HDI build-up steps. We think total layer count alone would understate the manufacturing work involved. Taiwan sell-side research points to a 3-28-3 HDI design for Trainium 4 in Q3 2027 and a 6-12-6 design for TPU v9 in Q4 2027. That works out to 34 total layers for Trainium 4 and 24 for TPU v9. But TPU v9 would have six HDI build-up layers on each side of its inner stack, versus three for Trainium 4. Those outer layers are added through sequential lamination, with laser-drilled microvias connecting them. More build-up layers add processing steps and place greater demands on alignment and interconnect reliability. For AI PCB suppliers, the two designs would create different production requirements. High-layer-count capability and the ability to reliably manufacture deeper HDI structures both matter as cloud providers develop their next custom chips. $GOOG $AMZN