[Exclusive] Samsung Clears 70% Yield on HBM4E… All Out Push for HBM Supremacy Samsung Electronics, following the world's first mass production of sixth generation high bandwidth memory (HBM4), is now producing visible results in the development of HBM4E (seventh generation) and next generation DRAM as well. Song Jai Hyuk, Samsung Electronics' Chief Technology Officer and head of the Semiconductor Research Center, recently said at an internal management briefing that the reliability test yield (good product ratio) for HBM4E has risen to a level above 70 percent, and that the next generation 10 nanometer class seventh generation (D1d) DRAM process has secured an advantage over competitors. On this basis, Samsung Electronics is expected to further accelerate efforts to strengthen its next generation AI memory competitiveness. According to the semiconductor industry on the 1st, Song is reported to have said at the Device Solutions (DS) division internal management briefing held on June 30 that "the reliability test yield for HBM4E has risen to a level above 70 percent." The industry generally regards a yield of 80 percent or higher as the "mature yield" stage, at which a process is considered stabilized. Given that HBM4E is still at the reliability test stage, the level above 70 percent is seen as an indicator that development is entering a stable range. Samsung Electronics was the first in the industry to begin mass production shipments of HBM4 in February this year, and on May 29 it disclosed the detailed technical specifications of its 12 layer HBM4E product and shipped samples to major customers. HBM4 will be mounted on Nvidia's AI accelerator "Vera Rubin," set to launch in the second half of the year, and HBM4E, the successor to HBM4, is scheduled to be installed in next generation AI accelerators such as "Vera Rubin Ultra," which Nvidia plans to launch next year. The industry sees development for mass production progressing smoothly as sample evaluation by major customers moves forward. Next generation DRAM process development is also said to be proceeding well. Song assessed that D1d process technology competitiveness is ahead of competitors, and explained that development is underway with a target of Production Readiness Approval (PRA) in November. PRA is the final internal quality evaluation stage carried out ahead of product shipment. It is a procedure that comprehensively verifies yield, performance, and productivity to determine whether mass production is feasible, and passing it enables a full transition to a mass production system. In particular, D1d is the core DRAM process that Samsung Electronics plans to apply starting from the next generation HBM5 (eighth generation). The industry expects that if D1d development proceeds as planned, it will have a positive effect not only on next generation DRAM but also on the competitiveness of HBM5 and subsequent products. With HBM4E development results and D1d process stabilization coming together in this way, the view is that Samsung Electronics' technological competitiveness in the next generation AI memory race will be further strengthened. Meanwhile, following the briefing, complaints about the role and compensation structure of research and development personnel have also surfaced within the R&D organization. Members are said to have voiced the view that the contribution of the R&D organization needs to be recognized more actively. Earlier, Samsung Electronics' labor and management agreed to establish a "special management performance bonus" for the DS division, funded by 10.5 percent of business performance (operating profit). However, even within the same DS division, the bonus gap between the memory business and the common divisions including the research center, as well as the non memory (System LSI and Foundry) business units, is large, and calls for improvements to the compensation structure are growing louder.

To summarize GFHK's note: Rubin's SOCAMM2 has been nerfed once again — down to 64GB. But is that bearish? If anything, it's the opposite. Working off a 192GB SOCAMM2 configuration, NVIDIA had asked the memory makers for a corresponding volume of SOCAMM2 — and the memory makers came back telling them they could only supply 60–70% of that volume. This isn't a demand problem, it's a supply problem. The spec was cut because they couldn't get the SOCAMM2 supply. What about HBM? Contrary to what a certain research house published, Rubin Ultra is not being considered with 8Hi only. An HBM4E 12Hi SKU is also under consideration. It is a step down from the original 16Hi — but everyone already knew that, right? NVIDIA needs 12Hi if only to compete with AMD. The 8Hi is there to accommodate SKU requests from a subset of customers.

Korea, Eugene Investment & Securities: On the NVIDIA Rubin Ultra HBM despec NVIDIA appears to be discussing a plan to configure the main version of Rubin Ultra with a 2 die structure, HBM4 8Hi, and 8 stacks, and to add an HBM4E 8Hi version at a later point. Assuming NVIDIA's 2027 CoWoS capacity allocation is 1,200k, NVIDIA's accelerator output is estimated at 9.9M units and Rubin Ultra output at 1.6M units. If Rubin Ultra shifts from HBM4E 12Hi 384GB to HBM4 8Hi 192GB, NVIDIA's 2027 HBM demand would be revised down by roughly 10%, from 24.1bn Gb to 21.6bn Gb, and total HBM demand could decline by about 4%. Of course, this assumption does not reflect the possibility of a further expansion in accelerator output. That said, we judge this despec to be a strategy for producing more accelerators out of a limited pool of HBM bits, as the increase in HBM supply from DRAM makers has failed to keep pace with the speed of TSMC's front end and back end capacity expansion. DRAM makers find it difficult to expand HBM capacity flexibly because of the extreme shortage in commodity DRAM. With consumer set makers in smartphones and PCs experiencing production disruptions due to memory shortages, it is also not easy for memory makers to cut allocations to these customers any further.

Google and MediaTek Deepen TPU v9 Collaboration with Upgraded Triggerfish, Targeting AI Agents, Reinforcement Learning, and Effective Compute Maximization 1. My latest industry checks indicate that Google is developing an upgraded v9 chip, likely codenamed Triggerfish, based on TPU v9 / Humufish, with MediaTek exclusively securing this new, higher-priced order. 2. This upgraded chip is a Humufish-based follow-on program, positioned as a v9 variant with stronger inference capabilities that can help mitigate both the CPU wall and the memory wall. The project also further confirms MediaTek as Google’s preferred development partner for the TPU v9 generation. 3. The key differences between this v9 variant and Humufish are: SRAM capacity is significantly increased to 2–3 times that of Humufish, a new simulation die is added, and memory is upgraded to HBM4E, versus HBM4 on Humufish. 4. Beyond local TPU management and training / inference mode switching, the newly added simulation die's likely role centers on reinforcement learning (RL) and AI-agent coordination. 5. The larger SRAM keeps more of the active working set required by RL and AI agents local to the TPU, reducing data-movement costs and improving efficiency in the ultra-low-latency decode stage. 6. With Humufish lifetime shipments still estimated at 4–5 million units, Google is adding an incremental Triggerfish order of 1–2 million units, with production expected to begin in late 2027 and ramp in volume in 2028. As Triggerfish carries a unit price roughly 30% higher than Humufish, it could become an incremental driver of MediaTek’s 2028 business momentum.

Mizuho ASIC channel checks: pounding table on $AVGO "potential >35M TPU shipments in 2028E (up 8x from 2026E ~4.3M and 2025 ~2.4M), which is significantly above our estimates of ~7M ASIC shipments for AVGO" "We believe OAI ASIC is in development with 10GW AVGO project (Nexus) adding to TPU/MTIA/ARM roadmap." "Our call noted $ARM AI ASIC chip development ongoing as we continue to expect a launch in late-2026E/early-2027E" " $MU : With potential for TPU shipments to reach a cumulative 50M units in 2026-28E, we think ASICs could command an increasing share of the HBM market, especially as some of the next-gen ASICs move to HBM4e"

Nvidia got FAFOed multiple times with Rubin/Rubin Ultra design - They pushed for higher pin speed HBM4, but Micron's & Hynix's base die were subpar, so they had to change plans & face delays (lower pin speeds) - They pushed for a quad die Rubin Ultra design, yield and warpage issues forced them to switch to 2 die and 2+2 die MCM design - They pushed for 16 Hi HBM4E for Ultra, yield issues forced them to come back down to 12 Hi - They pushed for a dual profile 2.3kW/1.8kW Rubin, but indium-graphite TIM was unstable and now they are switching back to graphite TIM

Samsung Electronics Q2 Earnings Call Q&A Q. What is the supply mix between HBM and conventional DRAM? As stated during our previous earnings call, we manage our product mix independently of differences in profitability, with a focus on capturing AI-driven demand. We are applying the same approach to the growing demand for HBM. In particular, customer qualification for HBM4—a product drawing significant market attention—has progressed smoothly. We are rapidly expanding supply in line with customers’ ramp-up schedules in the second half of the year. Supported by increased 1c capacity and improved yields, we continue to expand our supply capabilities. As a result, HBM4 revenue in the third quarter is expected to more than triple quarter over quarter. For the second half as a whole, HBM4 is expected to account for well over 60% of our total HBM revenue. During the second half, we expect to increase our HBM market share to a level comparable to our overall DRAM market share, thereby achieving a balanced DRAM portfolio. (Translator’s note: Does this imply that Samsung expects to overtake SK hynix and become the No. 1 player in HBM market share?) Looking ahead to next year, we believe we have sufficient product competitiveness, based on the outcome of supply discussions with customers for 2027—which have already been completed—and our technological capabilities, as demonstrated by the industry’s first sampling of HBM4E. That said, we will continue to monitor the explosive growth in demand for general-purpose computing driven by agentic AI, as well as the relative growth of HBM and server DRAM. We will maintain an optimized product-mix strategy, targeting similar market-share levels in HBM and conventional DRAM to ensure a balanced portfolio.

Supply chain checks suggest the market may be massively underestimating HBM4 pricing power. HBM4 is around $15/GB this year. For 2027, checks point to potential pricing of $60/GB. That is not a normal memory upcycle. That is a 4x pricing reset in one of the most constrained components of AI infrastructure. If this plays out, SK hynix remains my highest-conviction HBM exposure: strongest HBM positioning, highest exposure, best customer alignment. Not financial advice. #sk# hynix

Rumor: SK hynix has run into an issue with its HBM4, requiring a photomask revision for the 12nm base die. As a result, volume shipments could be delayed by more than one quarter, which would also impact shipments across the related supply chain.