HBM4 and HBM4E are expected to nearly triple their share of HBM demand to 48% in 2027 as $NVDA Rubin and next-gen AI chips require a ton more advanced memory. What’s also wild is that HBM3E 8-Hi is expected to double its share to 17% suggesting ASICs are expanding the market and giving $MU and $SKHY more ways to grow across both premium and mature memory.

$MU $SKHY $DRAM Wow. HBM4E is now expected to consume about 4x (400%) more wafers per bit than conventional DRAM. Same fab capacity, same wafer starts, but a huge chunk of what used to become DDR is now becoming HBM instead. These are additional clues from Micron's Chief Business Officer at the KeyBanc Tech Forum that there is no end in sight for this DRAM shortage, even with every fab expansion announced. "To produce 100 bits of HBM, we have to reduce 300 bits of DDR supply because there is that 3 to 1 trade ratio between HBM3E and DDR. When you go to HBM4 and HBM4E, that trade ratio has worsened to closer to 4 to 1." So every 100 bits of HBM4E produced costs the industry roughly 400 bits of DDR supply. And HBM bit demand keeps climbing through 2030. Doesn't look like it's a temporary squeeze. Seems like a permanent reallocation of DRAM capacity toward HBM, and the trade ratio only gets worse from here. Structural Shift.

$MU just outlined plans for custom HBM4E in 2027 followed by 3D-stacked memory directly on AI processors in 2028 with new HBM generations planned nearly every year through 2030. That's a pretty big shift for Micron as memory becomes part of the AI chip itself.

$SKHY isn't cheaping out on HBM4E. SK Hynix's own words: "We are not reviewing assigning HBM4E base-die production to Intel." SH Hynix isn't stupid. You don't break the memory wall with a discount foundry. $MU $DRAM $TSM $INTC

[Exclusive] Samsung Clears 70% Yield on HBM4E… All Out Push for HBM Supremacy Samsung Electronics, following the world's first mass production of sixth generation high bandwidth memory (HBM4), is now producing visible results in the development of HBM4E (seventh generation) and next generation DRAM as well. Song Jai Hyuk, Samsung Electronics' Chief Technology Officer and head of the Semiconductor Research Center, recently said at an internal management briefing that the reliability test yield (good product ratio) for HBM4E has risen to a level above 70 percent, and that the next generation 10 nanometer class seventh generation (D1d) DRAM process has secured an advantage over competitors. On this basis, Samsung Electronics is expected to further accelerate efforts to strengthen its next generation AI memory competitiveness. According to the semiconductor industry on the 1st, Song is reported to have said at the Device Solutions (DS) division internal management briefing held on June 30 that "the reliability test yield for HBM4E has risen to a level above 70 percent." The industry generally regards a yield of 80 percent or higher as the "mature yield" stage, at which a process is considered stabilized. Given that HBM4E is still at the reliability test stage, the level above 70 percent is seen as an indicator that development is entering a stable range. Samsung Electronics was the first in the industry to begin mass production shipments of HBM4 in February this year, and on May 29 it disclosed the detailed technical specifications of its 12 layer HBM4E product and shipped samples to major customers. HBM4 will be mounted on Nvidia's AI accelerator "Vera Rubin," set to launch in the second half of the year, and HBM4E, the successor to HBM4, is scheduled to be installed in next generation AI accelerators such as "Vera Rubin Ultra," which Nvidia plans to launch next year. The industry sees development for mass production progressing smoothly as sample evaluation by major customers moves forward. Next generation DRAM process development is also said to be proceeding well. Song assessed that D1d process technology competitiveness is ahead of competitors, and explained that development is underway with a target of Production Readiness Approval (PRA) in November. PRA is the final internal quality evaluation stage carried out ahead of product shipment. It is a procedure that comprehensively verifies yield, performance, and productivity to determine whether mass production is feasible, and passing it enables a full transition to a mass production system. In particular, D1d is the core DRAM process that Samsung Electronics plans to apply starting from the next generation HBM5 (eighth generation). The industry expects that if D1d development proceeds as planned, it will have a positive effect not only on next generation DRAM but also on the competitiveness of HBM5 and subsequent products. With HBM4E development results and D1d process stabilization coming together in this way, the view is that Samsung Electronics' technological competitiveness in the next generation AI memory race will be further strengthened. Meanwhile, following the briefing, complaints about the role and compensation structure of research and development personnel have also surfaced within the R&D organization. Members are said to have voiced the view that the contribution of the R&D organization needs to be recognized more actively. Earlier, Samsung Electronics' labor and management agreed to establish a "special management performance bonus" for the DS division, funded by 10.5 percent of business performance (operating profit). However, even within the same DS division, the bonus gap between the memory business and the common divisions including the research center, as well as the non memory (System LSI and Foundry) business units, is large, and calls for improvements to the compensation structure are growing louder.