$MU $SKHY $DRAM Wow. HBM4E is now expected to consume about 4x (400%) more wafers per bit than conventional DRAM. Same fab capacity, same wafer starts, but a huge chunk of what used to become DDR is now becoming HBM instead. These are additional clues from Micron's Chief Business Officer at the KeyBanc Tech Forum that there is no end in sight for this DRAM shortage, even with every fab expansion announced. "To produce 100 bits of HBM, we have to reduce 300 bits of DDR supply because there is that 3 to 1 trade ratio between HBM3E and DDR. When you go to HBM4 and HBM4E, that trade ratio has worsened to closer to 4 to 1." So every 100 bits of HBM4E produced costs the industry roughly 400 bits of DDR supply. And HBM bit demand keeps climbing through 2030. Doesn't look like it's a temporary squeeze. Seems like a permanent reallocation of DRAM capacity toward HBM, and the trade ratio only gets worse from here. Structural Shift.

$SKHY isn't cheaping out on HBM4E. SK Hynix's own words: "We are not reviewing assigning HBM4E base-die production to Intel." SH Hynix isn't stupid. You don't break the memory wall with a discount foundry. $MU $DRAM $TSM $INTC

[Exclusive] Samsung Clears 70% Yield on HBM4E… All Out Push for HBM Supremacy Samsung Electronics, following the world's first mass production of sixth generation high bandwidth memory (HBM4), is now producing visible results in the development of HBM4E (seventh generation) and next generation DRAM as well. Song Jai Hyuk, Samsung Electronics' Chief Technology Officer and head of the Semiconductor Research Center, recently said at an internal management briefing that the reliability test yield (good product ratio) for HBM4E has risen to a level above 70 percent, and that the next generation 10 nanometer class seventh generation (D1d) DRAM process has secured an advantage over competitors. On this basis, Samsung Electronics is expected to further accelerate efforts to strengthen its next generation AI memory competitiveness. According to the semiconductor industry on the 1st, Song is reported to have said at the Device Solutions (DS) division internal management briefing held on June 30 that "the reliability test yield for HBM4E has risen to a level above 70 percent." The industry generally regards a yield of 80 percent or higher as the "mature yield" stage, at which a process is considered stabilized. Given that HBM4E is still at the reliability test stage, the level above 70 percent is seen as an indicator that development is entering a stable range. Samsung Electronics was the first in the industry to begin mass production shipments of HBM4 in February this year, and on May 29 it disclosed the detailed technical specifications of its 12 layer HBM4E product and shipped samples to major customers. HBM4 will be mounted on Nvidia's AI accelerator "Vera Rubin," set to launch in the second half of the year, and HBM4E, the successor to HBM4, is scheduled to be installed in next generation AI accelerators such as "Vera Rubin Ultra," which Nvidia plans to launch next year. The industry sees development for mass production progressing smoothly as sample evaluation by major customers moves forward. Next generation DRAM process development is also said to be proceeding well. Song assessed that D1d process technology competitiveness is ahead of competitors, and explained that development is underway with a target of Production Readiness Approval (PRA) in November. PRA is the final internal quality evaluation stage carried out ahead of product shipment. It is a procedure that comprehensively verifies yield, performance, and productivity to determine whether mass production is feasible, and passing it enables a full transition to a mass production system. In particular, D1d is the core DRAM process that Samsung Electronics plans to apply starting from the next generation HBM5 (eighth generation). The industry expects that if D1d development proceeds as planned, it will have a positive effect not only on next generation DRAM but also on the competitiveness of HBM5 and subsequent products. With HBM4E development results and D1d process stabilization coming together in this way, the view is that Samsung Electronics' technological competitiveness in the next generation AI memory race will be further strengthened. Meanwhile, following the briefing, complaints about the role and compensation structure of research and development personnel have also surfaced within the R&D organization. Members are said to have voiced the view that the contribution of the R&D organization needs to be recognized more actively. Earlier, Samsung Electronics' labor and management agreed to establish a "special management performance bonus" for the DS division, funded by 10.5 percent of business performance (operating profit). However, even within the same DS division, the bonus gap between the memory business and the common divisions including the research center, as well as the non memory (System LSI and Foundry) business units, is large, and calls for improvements to the compensation structure are growing louder.

At Hot Chips, SK Hynix confirmed hybrid bonding won't hit HBM4E. It's pushed to HBM5 (~2029-30). Not because the tech failed, it's proven since 2010 in image sensors. It's because bonding 16+ memory layers in a row is far harder than bonding one, and a JEDEC height rule just bought more time for the old method. More details here in my article:

HBM supply vs demand gab in Gigabits. What you must understand: -That -7% bit shortfall is really a -21% to -28% wafer shortfall for HBM4E. It eats 3x to 4x more wafers per bit due to TSV and very low stack yields. -The gap went from -1% to -7%. It's widening even as all 3 giants pour resources and wafer starts into HBM. That's a breakout. -2027 new supply is already sold out. The memory trio is ramping with discipline, and SK Hynix's chairman doesn't see balance returning even by 2030.

- Global Unichip Corp. (GUC, has announced a 16 Gbps HBM4E PHY and Controller IP on TSMC N2P, targeting next-generation AI ASICs with support for CoWoS and 3D SoIC architectures. - Importantly, the 2nm designation refers to the ASIC-side HBM PHY and Controller IP implemented on TSMC N2P, not the DRAM process used to manufacture the HBM4E memory itself. - GUC says the HBM4E PHY and Controller design has been finalized and has already been adopted by a customer's AI ASIC, although the customer has not been disclosed. - The previous 12 Gbps HBM4 PHY and Controller on TSMC N3P is already silicon-proven, with GUC now extending the platform to 16 Gbps HBM4E. - GUC CTO Igor Elkanovich says its HBM4E solution delivers 3.3x bandwidth, 2.6x area efficiency, and 1.4x power efficiency versus HBM3E, based on GUC's IP comparison. - The platform goes beyond conventional CoWoS HBM connectivity by supporting a face-up HBM PHY for TSMC SoIC-X, including TSVs for I/O, power, ground, and feedthrough power delivery to logic dies stacked above the PHY. - GUC is positioning HBM4E together with face-up UCIe and GLink-3D as a broader 3D ASIC interface platform, enabling integration across HBM, chiplets, and vertically stacked logic. - The timing is notable because SK hynix announced in June 2026 that it had shipped 12-layer HBM4E samples operating at up to 16 Gbps per pin to major customers, meaning both the memory and ASIC/IP ecosystems are now preparing for the same performance generation.

HBM: keep >40% revenue share next year. FY27 blended ASP now +48% y/y (was +35%). 8Hi mix seen at 55–60% as key customers lean 8Hi over 12Hi on HBM4 / HBM4E. Undersupply through FY28. $SKHY

SK hynix sharply raises share of leading edge DRAM… 1c to become main process early next year SK hynix is rapidly expanding the production share of its sixth generation 10nm class (1c) DRAM. With 1c DRAM set to serve as the core die stacked into next generation high bandwidth memory (HBM4E), the company appears to be accelerating its process transition. As demand for high value added memory for servers and artificial intelligence (AI) grows, the race with Samsung Electronics and Micron to migrate to finer process nodes is also heating up. "1c process share expected to exceed 34% within the year" According to industry sources on the 7th, SK hynix's 1c DRAM share rose from around 10% in the first quarter of this year to the 13% range in the second quarter. It is projected to reach the 24% range in the third quarter and the 34% range in the fourth quarter. In the first quarter of next year, the 1c share is expected to climb to the 35% range, overtaking 1b (33% range) for the first time and becoming the company's main process. The share of 1b (fifth generation 10nm class) DRAM was found to have peaked at the 43% range in the second quarter of this year and turned downward. As the production shift to 1c gets into full swing, the share of older generation processes is shrinking in sequence. Industry estimates show that, as of the end of the second quarter, Samsung Electronics' 1c share stood in the 16% range and Micron's in the 19% range, somewhat ahead of SK hynix (13% range). However, with SK hynix stepping up the pace of its transition in the second half of this year, it is expected to overtake Samsung Electronics (31% range) on a fourth quarter basis (34% range). On its second quarter earnings conference call last month, SK hynix said that supply of DRAM built on the sixth generation 10nm class (1c) process had begun in earnest in the second quarter. The company projected that bit growth (the rate of increase in production volume) in the second half of this year would exceed the first half, driven by expanding HBM4 (sixth generation HBM) volumes and rising shipments of 1c based commodity DRAM. Process transition in preparation for HBM4E performance gains The battle for HBM4 leadership between Samsung Electronics and SK hynix is also intertwined with the pace of the 1c transition. Samsung Electronics is applying 1c DRAM from the HBM4 stage onward and is touting top tier performance with operating speeds of around 11.7Gbps. SK hynix, by contrast, chose a strategy that prioritizes mass production stability, relying on its proven 1b DRAM and advanced MR-MUF packaging technology, and is applying 1c DRAM as the core HBM die for the first time starting with next generation HBM4E (seventh generation HBM). Industry observers say this difference in strategy is being reflected in the two companies' market shares. Major research firms including Counterpoint Research project this year's HBM4 market share, on a combined basis across NVIDIA, Google, AMD and others, at the mid 50% range for SK hynix, the high 20% range for Samsung Electronics, and the high 10% range for Micron. The picture is one in which SK hynix holds its volume advantage on the strength of mass production stability, while Samsung Electronics seeks to expand share through a technical spec advantage. Against this backdrop, analysts say SK hynix's push to speed up the 1c transition will translate into tangible benefits in cost and productivity, beyond simply shrinking the node. Since bit output per wafer rises compared with the previous generation, more bits are produced from the same wafer input, improving cost competitiveness, which is cited as a factor that will help defend DRAM segment profitability from the second half onward. With the 1c transition proceeding alongside a growing mix of high value added products for servers and HBM, analysts say productivity gains are highly likely to feed directly into margin improvement. An official in the semiconductor industry said, "The pace of the 1c transition itself is encouraging, but it only becomes meaningful if actual production yields and customer qualification schedules back it up," adding, "Starting with HBM4E, the fine process competition between Samsung Electronics and SK hynix will intensify further."